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[libreriscv.git] / openpower / sv / svp64.mdwn

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 8a591abb37ac5be152a969aa132446feed720ae5..2734a7cf17da6e006e183662b2ead183ed731deb 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -505,9 +505,9 @@ EXTRA is the means by which two things are achieved:
 
 The register files are therefore extended:
 
-* INT is extended from r0-31 to 128
-* FP is extended from fp0-32 to 128
-* CR is extended from CR0-7 to CR0-127
+* INT is extended from r0-31 to r0-127
+* FP is extended from fp0-32 to fp0-fp127
+* CR Fields are extended from CR0-7 to CR0-127
 
 In the following tables register numbers are constructed from the
 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2