+[[!tag standards]]
+
# SVP64 for OpenPOWER ISA v3.0B
-This document describes SV augmentation of the OpenPOWER v3.0B ISA. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the OpenPOWER Foundation (only v3.0B)
+**DRAFT STATUS**
+
+This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
Links:
* [[svp64/appendix]]
* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
* <https://bugs.libre-soc.org/show_bug.cgi?id=550>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
+* <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
Table of contents
# Introduction
-This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It it best read in conjunction with the [[sv/overview]] which explains the background.
+This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It is best read in conjunction with the [[sv/overview]] which explains the background.
The plan is to create an encoding for SVP64, then to create an encoding
for SVP48, then to reorganize them both to improve field overlap,
For the new fields added in SVP64, instructions that have any of their
fields set to a reserved value must cause an illegal instruction trap,
-to allow emulation of future instruction sets.
+to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
## Prefix Fields
-To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
+To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
(see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
This is achieved by setting bits 7 and 9 to 1:
| 0:5 | 6 | 7 | 8 | 9 | 10:31 |
|--------|-------|---|-------|---|----------|
| EXT01 | RM | 1 | RM | 1 | RM |
-| 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
+| 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
instruction. That instruction becomes "prefixed" with the SVP context: the
Remapped Encoding field (RM).
-# Remapped Encoding Fields
-
-Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
-variants. There are two categories: Single and Twin Predication.
-Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
-
-* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
-* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
-* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
-* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
-
-## Common RM fields
+# Common RM fields
The following fields are common to all Remapped Encodings:
-
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
-| MASK\_KIND | `0` | Execution (predication) Mask Kind |
+| MASKMODE | `0` | Execution (predication) Mask Kind |
| MASK | `1:3` | Execution Mask |
| ELWIDTH | `4:5` | Element Width |
-| SUBVL | `6:7` | Sub-vector length |
-| MODE | `19:23` | changes Vector behaviour |
-
-Bits 9 to 18 are further decoded depending on RM category for the instruction.
-
-## RM-1P-3S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------------------|
-| Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
-| reserved | `16` | reserved |
-
-## RM-1P-2S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|-------------------------------------------|
-| Rdest\_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 |
-| Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-These are for 2 operand 1 dest instructions, such as `add RT, RA,
-RB`. However also included are unusual instructions with an implicit dest
-that is identical to its src reg, such as `rlwinmi`.
-
-Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
-an alternative destination. With SV however this becomes possible.
-Therefore, the fact that the dest is implicitly also a src should not
-mislead: due to the *prefix* they are different SV regs.
+| ELWIDTH_SRC | `6:7` | Element Width for Source |
+| SUBVL | `8:9` | Sub-vector length |
+| MODE | `19:23` | changes Vector behaviour |
-* `rlwimi RA, RS, ...`
-* Rsrc1_EXTRA3 applies to RS as the first src
-* Rsrc2_EXTRA3 applies to RA as the secomd src
-* Rdest_EXTRA3 applies to RA to create an **independent** dest.
-
-With the addition of the EXTRA bits, the three registers
-each may be *independently* made vector or scalar, and be independently
-augmented to 7 bits in length.
+* MODE changes the behaviour of the SV operation (result saturation, mapreduce)
+* SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
+* ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
+* MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-## RM-2P-1S1D/2S
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
-
-## RM-2P-2S1D/1S2D/3S
-
-The primary purpose for this encoding is for Twin Predication on LOAD
-and STORE operations. see [[sv/ldst]] for detailed anslysis.
-
-RM-2P-2S1D:
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
-is in bits 8:9, Rdest1_EXTRA2 in 10:11)
-
-Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
-
-Note also that LD with update indexed, which takes 2 src and 2 dest
-(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
-Twin Predication. therefore these are treated as RM-2P-2S1D and the
-src spec for RA is also used for the same RA as a dest.
+Bits 10 to 18 are further decoded depending on RM category for the instruction.
+Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
* **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
*VL is altered as a result*.
* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping.
-* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see separate section below.
+* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]]
note that there are comprehensive caveats when using this mode.
* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
-Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
+Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
-The Mode table is laid out as follows:
+The Mode table for operations except LD/ST is laid out as follows:
| 0-1 | 2 | 3 4 | description |
| --- | --- |---------|-------------------------- |
* **N** sets signed/unsigned saturation.
**RC1** as if Rc=1, stores CRs *but not the result*
-# R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
-
-EXTRA is the means by which two things are achieved:
-
-1. Registers are marked as either Vector *or Scalar*
-2. Register field numbers (limited typically to 5 bit)
- are extended in range, both for Scalar and Vector.
-
-In the following tables register numbers are constructed from the
-standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
-interoperability between prefixing and nonprefixing of scalar registers
-is direct and convenient (when the EXTRA field is all zeros).
-
-A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
-
- if extra3_mode:
- spec = EXTRA3
- else:
- spec = EXTRA2 << 1 # same as EXTRA3, shifted
- if spec[2]: # vector
- return (RA << 2) | spec[0:1]
- else: # scalar
- return (spec[0:1] << 5) | RA
+## LD/ST ffirst
-## INT/FP EXTRA3
-
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming). also, these are the
-encodings used in the original SV Prefix scheme. the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
-
-| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
-|-----------|-------|---------------|---------------------|
-| 000 | Scalar | `r0-r31` | `0b00 RA` |
-| 001 | Scalar | `r32-r63` | `0b01 RA` |
-| 010 | Scalar | `r64-r95` | `0b10 RA` |
-| 011 | Scalar | `r96-r127` | `0b11 RA` |
-| 100 | Vector | `r0-r124` | `RA 0b00` |
-| 101 | Vector | `r1-r125` | `RA 0b01` |
-| 110 | Vector | `r2-r126` | `RA 0b10` |
-| 111 | Vector | `r3-r127` | `RA 0b11` |
-
-## INT/FP EXTRA2
-
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
-
-| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
-|-----------|-------|---------------|---------------------|
-| 00 | Scalar | `r0-r31` | `0b00 RA` |
-| 01 | Scalar | `r32-r63` | `0b01 RA` |
-| 10 | Vector | `r0-r124` | `RA 0b00` |
-| 11 | Vector | `r2-r126` | `RA 0b10` |
-
-## CR EXTRA3
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
- Encoding shown MSB down to LSB
-
-| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|------|---------| --------|---------|
-| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
-| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
-| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
-| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
-
-## CR EXTRA2
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
-Encoding shown MSB down to LSB
-
-| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|--------|---------|---------|---------|
-| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+ffirst LD/ST to multiple pages via a Vectorised base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore in these special circumstances requesting ffirst with a vector base is instead interpreted as element-strided LD/ST. See <https://bugs.libre-soc.org/show_bug.cgi?id=561>
+and [[sv/ldst]]
# ELWIDTH Encoding
Default behaviour is set to 0b00 so that zeros follow the convention of
-"npt doing anything". In this case it means that elwidth overrides
+`scalar identity behaviour`. In this case it means that elwidth overrides
are not applicable. Thus if a 32 bit instruction operates on 32 bit,
`elwidth=0b00` specifies that this behaviour is unmodified. Likewise
when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
| Value | Mnemonic | Description |
|-------|----------------|------------------------------------|
| 00 | DEFAULT | default behaviour for operation |
-| 01 | `ELWIDTH=b` | Byte: 8-bit integer |
+| 01 | `ELWIDTH=w` | Word: 32-bit integer |
| 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
-| 11 | `ELWIDTH=w` | Word: 32-bit integer |
+| 11 | `ELWIDTH=b` | Byte: 8-bit integer |
+
+This encoding is chosen such that the byte width may be computed as `(3-ew)<<8`
## Elwidth for FP Registers:
| Value | Mnemonic | Description |
|-------|----------------|------------------------------------|
| 00 | DEFAULT | default behaviour for FP operation |
-| 01 | `ELWIDTH=bf16` | Reserved for `bf16` |
+| 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
| 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
-| 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
+| 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
Note:
[`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
TODO, important, particularly for crops, mfcr and mtcr, what elwidth
even means. instead it may be possible to use the bits as extra indices
-(EXTRA6) to access the full 64 CRs. TBD, several ideas
+(add to EXTRA2/3) to access the full 128 CRs at the bit level. TBD, several ideas
The actual width of the CRs cannot be altered: they are 4 bit. Also,
for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
Examples: mfxm may take the extra bits and use them as extra mask bits.
+Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
+
# SUBVL Encoding
the default for SUBVL is 1 and its encoding is 0b00 to indicate that
sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
this may be considered to be elements 0b00 to 0b01 inclusive.
-# MASK/MASK_SRC & MASK_KIND Encoding
+# MASK/MASK_SRC & MASKMODE Encoding
+
+TODO: rename MASK_KIND to MASKMODE
One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
types may not be mixed.
-Special note: to get default behaviour (SV disabled) this field must
+Special note: to disable predication this field must
be set to zero in combination with Integer Predication also being set
to 0b000. this has the effect of enabling "all 1s" in the predicate
mask, which is equivalent to "not having any predication at all"
and consequently, in combination with all other default zeros, fully
-disables SV.
+disables SV (`scalar identity behaviour`).
+
+`MASKMODE` may be set to one of 2 values:
| Value | Description |
-|-------|------------------------------------------------------|
-| 0 | MASK/MASK_SRC are encoded using Integer Predication |
-| 1 | MASK/MASK_SRC are encoded using CR-based Predication |
+|-----------|------------------------------------------------------|
+| 0 | MASK/MASK_SRC are encoded using Integer Predication |
+| 1 | MASK/MASK_SRC are encoded using CR-based Predication |
Integer Twin predication has a second set of 3 bits that uses the same
encoding thus allowing either the same register (r3 or r10) to be used
Likewise CR based twin predication has a second set of 3 bits, allowing
a different test to be applied.
-## Integer Predication (MASK_KIND=0)
+## Integer Predication (MASKMODE=0)
When the predicate mode bit is zero the 3 bits are interpreted as below.
Twin predication has an identical 3 bit field similarly encoded.
+`MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
+
| Value | Mnemonic | Element `i` enabled if: |
|-------|----------|------------------------------|
| 000 | ALWAYS | predicate effectively all 1s |
| 110 | R30 | `R30 & (1 << i)` is non-zero |
| 111 | ~R30 | `R30 & (1 << i)` is zero |
-## CR-based Predication (MASK_KIND=1)
+r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
+
+## CR-based Predication (MASKMODE=1)
When the predicate mode bit is one the 3 bits are interpreted as below.
-Twin predication has an identical 3 bit field similarly encoded
+Twin predication has an identical 3 bit field similarly encoded.
+
+`MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
| Value | Mnemonic | Element `i` is enabled if |
|-------|----------|--------------------------|
`offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
+Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
+
+# Extra Remapped Encoding
+
+Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
+
+There are two categories: Single and Twin Predication.
+Due to space considerations further subdivision of Single Predication
+is based on whether the number of src operands is 2 or 3.
+
+* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
+* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
+* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
+* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
+* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
+
+## RM-1P-3S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
+| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
+| reserved | `18` | reserved |
+
+## RM-1P-2S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|-------------------------------------------|
+| Rdest\_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
+| Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
+
+These are for 2 operand 1 dest instructions, such as `add RT, RA,
+RB`. However also included are unusual instructions with an implicit dest
+that is identical to its src reg, such as `rlwinmi`.
+
+Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
+an alternative destination. With SV however this becomes possible.
+Therefore, the fact that the dest is implicitly also a src should not
+mislead: due to the *prefix* they are different SV regs.
+
+* `rlwimi RA, RS, ...`
+* Rsrc1_EXTRA3 applies to RS as the first src
+* Rsrc2_EXTRA3 applies to RA as the secomd src
+* Rdest_EXTRA3 applies to RA to create an **independent** dest.
+
+With the addition of the EXTRA bits, the three registers
+each may be *independently* made vector or scalar, and be independently
+augmented to 7 bits in length.
+
+## RM-2P-1S1D/2S
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
+| MASK_SRC | `16:18` | Execution Mask for Source |
+
+`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+
+## RM-2P-2S1D/1S2D/3S
+
+The primary purpose for this encoding is for Twin Predication on LOAD
+and STORE operations. see [[sv/ldst]] for detailed anslysis.
+
+RM-2P-2S1D:
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| MASK_SRC | `16:18` | Execution Mask for Source |
+
+Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
+is in bits 10:11, Rdest1_EXTRA2 in 12:13)
+
+Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
+
+Note also that LD with update indexed, which takes 2 src and 2 dest
+(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
+Twin Predication. therefore these are treated as RM-2P-2S1D and the
+src spec for RA is also used for the same RA as a dest.
+
+Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
+
+# R\*\_EXTRA2/3
+
+EXTRA is the means by which two things are achieved:
+
+1. Registers are marked as either Vector *or Scalar*
+2. Register field numbers (limited typically to 5 bit)
+ are extended in range, both for Scalar and Vector.
+
+The register files are therefore extended:
+
+* INT is extended from r0-31 to 128
+* FP is extended from fp0-32 to 128
+* CR is extended from CR0-7 to CR0-127
+
+In the following tables register numbers are constructed from the
+standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
+or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
+interoperability between prefixing and nonprefixing of scalar registers
+is direct and convenient (when the EXTRA field is all zeros).
+
+A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
+
+ if extra3_mode:
+ spec = EXTRA3
+ else:
+ spec = EXTRA2 << 1 # same as EXTRA3, shifted
+ if spec[2]: # vector
+ return (RA << 2) | spec[0:1]
+ else: # scalar
+ return (spec[0:1] << 5) | RA
+
+Future versions may extend to 256 by shifting Vector numbering up.
+Scalar will not be altered.
+
+## INT/FP EXTRA3
+
+alternative which is understandable and, if EXTRA3 is zero, maps to
+"no effect" (scalar OpenPOWER ISA field naming). also, these are the
+encodings used in the original SV Prefix scheme. the reason why they
+were chosen is so that scalar registers in v3.0B and prefixed scalar
+registers have access to the same 32 registers.
+
+Fields are as follows:
+
+* Value: R_EXTRA3
+* Mode: register is tagged as scalar or vector
+* Range/Inc: the range of registers accessible from this EXTRA
+ encoding, and the "increment" (accessibility). "/4" means
+ that this EXTRA encoding may only give access (starting point)
+ every 4th register.
+* MSB..LSB: the bit field showing how the register opcode field
+ combines with EXTRA to give (extend) the register number (GPR)
+
+| Value | Mode | Range/Inc | 6..0 |
+|-----------|-------|---------------|---------------------|
+| 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
+| 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
+| 100 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 101 | Vector | `r1-r125`/4 | `RA 0b01` |
+| 110 | Vector | `r2-r126`/4 | `RA 0b10` |
+| 111 | Vector | `r3-r127`/4 | `RA 0b11` |
+
+## INT/FP EXTRA2
+
+alternative which is understandable and, if EXTRA2 is zero will map to
+"no effect" i.e Scalar OpenPOWER register naming:
+
+| R\*\_EXTRA2 | Mode | Range/inc | 6..0 |
+|-----------|-------|---------------|-----------|
+| 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 10 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 11 | Vector | `r2-r126`/4 | `RA 0b10` |
+
+## CR EXTRA3
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
+
+ Encoding shown MSB down to LSB
+
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|------|---------------|-----------| --------|---------|
+| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
+| 011 | Scalar | `CR24-CR32`/1 | 0b0011 | BA[4:2] | BA[1:0] |
+| 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
+| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
+
+## CR EXTRA2
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+
+Encoding shown MSB down to LSB
+
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|--------|----------------|---------|---------|---------|
+| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+
# Appendix
Now at its own page: [[svp64/appendix]]
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