TODO, important, particularly for crops, mfcr and mtcr, what elwidth
even means. instead it may be possible to use the bits as extra indices
-(add to EXTRA2/3) to access the full 64 CRs at the bit level. TBD, several ideas
+(add to EXTRA2/3) to access the full 128 CRs at the bit level. TBD, several ideas
The actual width of the CRs cannot be altered: they are 4 bit. Also,
for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
2. Register field numbers (limited typically to 5 bit)
are extended in range, both for Scalar and Vector.
+The register files are therefore extended:
+
+* INT is extended from r0-31 to 128
+* FP is extended from fp0-32 to 128
+* CR is extended from CR0-7 to CR0-127
+
In the following tables register numbers are constructed from the
standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
else: # scalar
return (spec[0:1] << 5) | RA
+Future versions may extend to 256 by shifting Vector numbering up.
+Scalar will not be altered.
+
## INT/FP EXTRA3
alternative which is understandable and, if EXTRA3 is zero, maps to
were chosen is so that scalar registers in v3.0B and prefixed scalar
registers have access to the same 32 registers.
-| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
+Fields are as follows:
+
+* Value: R_EXTRA3
+* Mode: register is tagged as scalar or vector
+* Range/Inc: the range of registers accessible from this EXTRA
+ encoding, and the "increment" (accessibility). "/4" means
+ that this EXTRA encoding may only give access (starting point)
+ every 4th register.
+* MSB..LSB: the bit field showing how the register opcode field
+ combines with EXTRA to give (extend) the register number (GPR)
+
+| Value | Mode | Range/Inc | 6..0 |
|-----------|-------|---------------|---------------------|
-| 000 | Scalar | `r0-r31` | `0b00 RA` |
-| 001 | Scalar | `r32-r63` | `0b01 RA` |
-| 010 | Scalar | `r64-r95` | `0b10 RA` |
-| 011 | Scalar | `r96-r127` | `0b11 RA` |
-| 100 | Vector | `r0-r124` | `RA 0b00` |
-| 101 | Vector | `r1-r125` | `RA 0b01` |
-| 110 | Vector | `r2-r126` | `RA 0b10` |
-| 111 | Vector | `r3-r127` | `RA 0b11` |
+| 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
+| 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
+| 100 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 101 | Vector | `r1-r125`/4 | `RA 0b01` |
+| 110 | Vector | `r2-r126`/4 | `RA 0b10` |
+| 111 | Vector | `r3-r127`/4 | `RA 0b11` |
## INT/FP EXTRA2
alternative which is understandable and, if EXTRA2 is zero will map to
"no effect" i.e Scalar OpenPOWER register naming:
-| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
-|-----------|-------|---------------|---------------------|
-| 00 | Scalar | `r0-r31` | `0b00 RA` |
-| 01 | Scalar | `r32-r63` | `0b01 RA` |
-| 10 | Vector | `r0-r124` | `RA 0b00` |
-| 11 | Vector | `r2-r126` | `RA 0b10` |
+| R\*\_EXTRA2 | Mode | Range/inc | 6..0 |
+|-----------|-------|---------------|-----------|
+| 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 10 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 11 | Vector | `r2-r126`/4 | `RA 0b10` |
## CR EXTRA3
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
Encoding shown MSB down to LSB
-| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|------|---------| --------|---------|
-| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
-| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
-| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
-| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|------|---------------|-----------| --------|---------|
+| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
+| 011 | Scalar | `CR24-CR32`/1 | 0b0011 | BA[4:2] | BA[1:0] |
+| 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
+| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
## CR EXTRA2
Encoding shown MSB down to LSB
-| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|--------|---------|---------|---------|
-| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|--------|----------------|---------|---------|---------|
+| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
# Appendix
projects / libreriscv.git / blobdiff