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[libreriscv.git] / openpower / sv / svp64.mdwn

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 89a32e7b0c992ab5728cf4584c002ee63d94f70e..549e98ddb5dfec68e2dd7983f743601a87d0fe27 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -226,8 +226,8 @@ than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
 * **RC1** as if Rc=1, stores CRs *but not the result*
 * **VLi** VL inclusive: in fail-first mode, the truncation of
- VL *includes* the current element at the failure point rather
- than excludes it from the count.
+  VL *includes* the current element at the failure point rather
+  than excludes it from the count.
 
 For LD/ST Modes, see [[sv/ldst]].  For Branch modes, see [[sv/branches]] Immediate and Indexed LD/ST
 are both different, in order to support a large range of features
@@ -269,6 +269,9 @@ Note:
 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
 is reserved for a future implementation of SV
 
+Note that any operation in Power ISA ending in "s" (`fadds`) shall
+perform its operation at **half** the ELWIDTH.  `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32.
+
 ## Elwidth for CRs:
 
 TODO, important, particularly for crops, mfcr and mtcr, what elwidth