It is important to note that unlike v3.1 64-bit prefixed instructions
there is insufficient space in `RM` to provide identification of
any SVP64 Fields without first partially decoding the
-32-bit suffix. Extreme caution and care must therefore be taken
+32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
+`RM` format is individually associated with every instruction.
+
+Extreme caution and care must therefore be taken
when extending SVP64 in future, to not create unnecessary relationships
between prefix and suffix that could complicate decoding, adding latency.
to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
then padded back out to fit in IEEE754 FP64, exactly as for Scalar
-v3.0B "single" FP.
+v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
+or ELWIDTH=bf16 is reserved and must raise an illegal instruction
+(IEEE754 FP8 or BF8 are not defined).
## Elwidth for CRs:
The register files are therefore extended:
-* INT is extended from r0-31 to 128
-* FP is extended from fp0-32 to 128
-* CR is extended from CR0-7 to CR0-127
+* INT is extended from r0-31 to r0-127
+* FP is extended from fp0-32 to fp0-fp127
+* CR Fields are extended from CR0-7 to CR0-127
In the following tables register numbers are constructed from the
standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
+or EXTRA3 field from the SV Prefix, determined by the specific
+RM-xx-yyyy designation for a given instruction.
+The prefixing is arranged so that
interoperability between prefixing and nonprefixing of scalar registers
is direct and convenient (when the EXTRA field is all zeros).
Future versions may extend to 256 by shifting Vector numbering up.
Scalar will not be altered.
+Note that in some cases the range of starting points for Vectors
+is limited.
+
## INT/FP EXTRA3
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming). also, these are the
-encodings used in the original SV Prefix scheme. the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
+If EXTRA3 is zero, maps to
+"scalar identity" (scalar OpenPOWER ISA field naming).
Fields are as follows:
## INT/FP EXTRA2
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
+If EXTRA2 is zero will map to
+"scalar identity behaviour" i.e Scalar OpenPOWER register naming:
| Value | Mode | Range/inc | 6..0 |
|-----------|-------|---------------|-----------|
| 10 | Vector | `r0-r124`/4 | `RA 0b00` |
| 11 | Vector | `r2-r126`/4 | `RA 0b10` |
-## CR EXTRA3
+## CR Field EXTRA3
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
+CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR4, CR8, CR12, CR16...
- Encoding shown MSB down to LSB
+Encoding shown MSB down to LSB
+
+For a 5-bit operand (BA, BB, BT):
| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
|-------|------|---------------|-----------| --------|---------|
| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
+For a 3-bit operand (e.g. BFA):
+
+| Value | Mode | Range/Inc | 6..3 | 2..0 |
+|-------|------|---------------|-----------| --------|
+| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
+| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
+| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
+| 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
+| 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
+| 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
+| 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
+| 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
+
## CR EXTRA2
CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
+
Encoding shown MSB down to LSB
+For a 5-bit operand (BA, BB, BC):
+
| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
|-------|--------|----------------|---------|---------|---------|
| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+For a 3-bit operand (e.g. BFA):
+
+| Value | Mode | Range/Inc | 6..3 | 2..0 |
+|-------|------|---------------|-----------| --------|
+| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
+| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
+| 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
+| 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
+
# Appendix
Now at its own page: [[svp64/appendix]]
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