[[!tag standards]]
-# SVP64 for OpenPOWER ISA v3.0B
+# DRAFT SVP64 for OpenPOWER ISA v3.0B
-**DRAFT STATUS**
+* **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
-This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
+This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. It is in Draft Status and
+will be submitted to the [[!wikipedia OpenPOWER_Foundation]] ISA WG
+via the External RFC Process.
+
+Credits and acknowledgements:
+
+* Luke Leighton
+* Jacob Lifshay
+* Hendrik Boom
+* Richard Wilbur
+* Alexandre Oliva
+* Cesar Strauss
+* NLnet Foundation, for funding
+* OpenPOWER Foundation
+* Paul Mackerras
+* Toshaan Bharvani
+* IBM for the Power ISA itself
Links:
This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
-The plan is to create an encoding for SVP64, then to create an encoding
-for SVP48, then to reorganize them both to improve field overlap,
-reducing the amount of decoder hardware necessary.
-
All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
and counting up as you move to the LSB end). All bit ranges are inclusive
(so `4:6` means bits 4, 5, and 6).
svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
+Subset implementations in hardware are permitted, as long as certain
+rules are followed, allowing for full soft-emulation including future
+revisions. Details in the [[svp64/appendix]].
+
## SVP64 encoding features
A number of features need to be compacted into a very small space of only 24 bits:
* Independent per-register Scalar/Vector tagging and range extension on every register
* Element width overrides on both source and destination
* Predication on both source and destination
-* Two different *types* of predication: INT and CR
-* SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
+* Two different sources of predication: INT and CR Fields
+* SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
predicate-result mode.
This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
For the new fields added in SVP64, instructions that have any of their
fields set to a reserved value must cause an illegal instruction trap,
-to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
+to allow emulation of future instruction sets, or for subsets of SVP64
+to be implemented in hardware and the rest emulated.
+This includes SVP64 SPRs: reading or writing values which are not
+supported in hardware must also raise illegal instruction traps
+in order to allow emulation.
+Unless otherwise stated, reserved values are always all zeros.
-This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
+This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
+is intended the red keyword `RESERVED` is used.
-# Identity Behaviour
+# Scalar Identity Behaviour
SVP64 is designed so that when the prefix is all zeros, and
VL=1, no effect or
influence occurs (no augmentation) such that all standard OpenPOWER
-v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
+v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
- whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
-
-The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
+ whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
# Register Naming and size
| EXT01 | RM | 1 | RM | 1 | RM |
| 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
-Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
+Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
instruction. That instruction becomes "prefixed" with the SVP context: the
Remapped Encoding field (RM).
+It is important to note that unlike v3.1 64-bit prefixed instructions
+there is insufficient space in `RM` to provide identification of
+any SVP64 Fields without first partially decoding the
+32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
+`RM` format is individually associated with every instruction.
+
+Extreme caution and care must therefore be taken
+when extending SVP64 in future, to not create unnecessary relationships
+between prefix and suffix that could complicate decoding, adding latency.
+
# Common RM fields
The following fields are common to all Remapped Encodings:
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
-| MASKMODE | `0` | Execution (predication) Mask Kind |
-| MASK | `1:3` | Execution Mask |
+| MASKMODE | `0` | Execution (predication) Mask Kind |
+| MASK | `1:3` | Execution Mask |
+| SUBVL | `8:9` | Sub-vector length |
+
+The following fields are optional or encoded differently depending
+on context after decoding of the Scalar suffix:
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
| ELWIDTH | `4:5` | Element Width |
| ELWIDTH_SRC | `6:7` | Element Width for Source |
-| SUBVL | `8:9` | Sub-vector length |
+| EXTRA | `10:18` | Register Extra encoding |
| MODE | `19:23` | changes Vector behaviour |
* MODE changes the behaviour of the SV operation (result saturation, mapreduce)
* SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
* ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
* MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
+* Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
-Bits 10 to 18 are further decoded depending on RM category for the instruction.
-Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
+Similar to OpenPOWER `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
Mode is an augmentation of SV behaviour. Different types of
instructions have different needs, similar to Power ISA
v3.1 64 bit prefix 8LS and MTRR formats apply to different
-instruction types
+instruction types. Modes include Reduction, Iteration, arithmetic
+saturation, and Fail-First. More specific details in each
+section and in the [[svp64/appendix]]
* For condition register operations see [[sv/cr_ops]]
* For LD/ST Modes, see [[sv/ldst]].
[`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
is reserved for a future implementation of SV
-Note that any operation in Power ISA ending in "s" (`fadds`) shall
-perform its operation at **half** the ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32.
+Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
+perform its operation at **half** the ELWIDTH then padded back out
+to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
+clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
+then padded back out to fit in IEEE754 FP64, exactly as for Scalar
+v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
+or ELWIDTH=bf16 is reserved and must raise an illegal instruction
+(IEEE754 FP8 or BF8 are not defined).
## Elwidth for CRs:
-TODO, important, particularly for crops, mfcr and mtcr, what elwidth
-even means. instead it may be possible to use the bits as extra indices
-(add to EXTRA2/3) to access the full 128 CRs at the bit level. TBD, several ideas
-
-The actual width of the CRs cannot be altered: they are 4 bit. Also,
-for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
-the INT/FP result to which the elwidth override applies, *not* the CR.
-This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
+Element-width overrides for CR Fields has no meaning. The bits
+are therefore used for other purposes, or when Rc=1, the Elwidth
+applies to the result being tested, but not to the Vector of CR Fields.
-As mentioned TBD, this leaves crops etc. to have a meaning defined for
-elwidth, because these ops are pure explicit CR based.
-
-Examples: mfxm may take the extra bits and use them as extra mask bits.
-
-Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
# SUBVL Encoding
Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
+These mappings are part of the SVP64 Specification in exactly the same
+way as X-Form, D-Form. New Scalar instructions added to the Power ISA
+will need a corresponding SVP64 Mapping, which can be derived by-rote
+from examining the Register "Profile" of the instruction.
+
There are two categories: Single and Twin Predication.
Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
+is based on whether the number of src operands is 2 or 3. With only
+9 bits available some compromises have to be made.
* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
-| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
| Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
| Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
| Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
-| reserved | `18` | reserved |
+| EXTRA2_MODE | `18` | used by `divmod2du` and `madded` for RS |
+
+These are for 3 operand in and either 1 or 2 out instructions.
+3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
+such as `madded` have an implicit second destination, RS, the
+selection of which is determined by bit 18.
## RM-1P-2S1D
`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+## RM-1P-2S1D
+
+single-predicate, three registers (2 read, 1 write)
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
+| Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
+
## RM-2P-2S1D/1S2D/3S
The primary purpose for this encoding is for Twin Predication on LOAD
The register files are therefore extended:
-* INT is extended from r0-31 to 128
-* FP is extended from fp0-32 to 128
-* CR is extended from CR0-7 to CR0-127
+* INT is extended from r0-31 to r0-127
+* FP is extended from fp0-32 to fp0-fp127
+* CR Fields are extended from CR0-7 to CR0-127
In the following tables register numbers are constructed from the
standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
+or EXTRA3 field from the SV Prefix, determined by the specific
+RM-xx-yyyy designation for a given instruction.
+The prefixing is arranged so that
interoperability between prefixing and nonprefixing of scalar registers
is direct and convenient (when the EXTRA field is all zeros).
Future versions may extend to 256 by shifting Vector numbering up.
Scalar will not be altered.
+Note that in some cases the range of starting points for Vectors
+is limited.
+
## INT/FP EXTRA3
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming). also, these are the
-encodings used in the original SV Prefix scheme. the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
+If EXTRA3 is zero, maps to
+"scalar identity" (scalar OpenPOWER ISA field naming).
Fields are as follows:
## INT/FP EXTRA2
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
+If EXTRA2 is zero will map to
+"scalar identity behaviour" i.e Scalar OpenPOWER register naming:
| Value | Mode | Range/inc | 6..0 |
|-----------|-------|---------------|-----------|
| 10 | Vector | `r0-r124`/4 | `RA 0b00` |
| 11 | Vector | `r2-r126`/4 | `RA 0b10` |
-## CR EXTRA3
+## CR Field EXTRA3
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
+CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR4, CR8, CR12, CR16...
- Encoding shown MSB down to LSB
+Encoding shown MSB down to LSB
+
+For a 5-bit operand (BA, BB, BT):
| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
|-------|------|---------------|-----------| --------|---------|
| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
+For a 3-bit operand (e.g. BFA):
+
+| Value | Mode | Range/Inc | 6..3 | 2..0 |
+|-------|------|---------------|-----------| --------|
+| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
+| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
+| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
+| 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
+| 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
+| 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
+| 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
+| 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
+
## CR EXTRA2
CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
+
Encoding shown MSB down to LSB
+For a 5-bit operand (BA, BB, BC):
+
| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
|-------|--------|----------------|---------|---------|---------|
| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+For a 3-bit operand (e.g. BFA):
+
+| Value | Mode | Range/Inc | 6..3 | 2..0 |
+|-------|------|---------------|-----------| --------|
+| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
+| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
+| 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
+| 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
+
# Appendix
Now at its own page: [[svp64/appendix]]
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