# Introduction
-This document focuses on the encoding of [[SV|sv]], and assimes familiarity with the same. It it best read in conjunction with the [[sv/overview]] which explains the background.
+This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It is best read in conjunction with the [[sv/overview]] which explains the background.
The plan is to create an encoding for SVP64, then to create an encoding
for SVP48, then to reorganize them both to improve field overlap,
svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
+## SVP64 encoding features
+
+A number of features need to be compacted into a very small space of only 24 bits:
+
+* Independent per-register Scalar/Vector tagging and range extension on every register
+* Element width overrides on both source and destination
+* Predication on both source and destination
+* Two different *types* of predication: INT and CR
+* SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
+ predicate-result mode.
+
+This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
+
# Definition of Reserved in this spec.
For the new fields added in SVP64, instructions that have any of their
fields set to a reserved value must cause an illegal instruction trap,
-to allow emulation of future instruction sets.
+to allow emulation of future instruction sets. Reserved values are always all zeros.
This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
+The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
+
# Register Naming and size
SV Registers are simply the INT, FP and CR register files extended
## Prefix Fields
-To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
+To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
(see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
This is achieved by setting bits 7 and 9 to 1:
| 0:5 | 6 | 7 | 8 | 9 | 10:31 |
|--------|-------|---|-------|---|----------|
| EXT01 | RM | 1 | RM | 1 | RM |
-| 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
+| 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
instruction. That instruction becomes "prefixed" with the SVP context: the
Remapped Encoding field (RM).
-# Remapped Encoding Fields
-
-Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
-variants. There are two categories: Single and Twin Predication.
-Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
-
-* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
-* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
-* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
-* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
-
-## Common RM fields
+# Common RM fields
The following fields are common to all Remapped Encodings:
-
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
| MASK\_KIND | `0` | Execution (predication) Mask Kind |
| MASK | `1:3` | Execution Mask |
| ELWIDTH | `4:5` | Element Width |
-| SUBVL | `6:7` | Sub-vector length |
-| MODE | `19:23` | changes Vector behaviour |
-
-Bits 9 to 18 are further decoded depending on RM category for the instruction.
-
-## RM-1P-3S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------------------|
-| Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
-| reserved | `16` | reserved |
-
-## RM-1P-2S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|-------------------------------------------|
-| Rdest\_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 |
-| Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-These are for 2 operand 1 dest instructions, such as `add RT, RA,
-RB`. However also included are unusual instructions with an implicit dest
-that is identical to its src reg, such as `rlwinmi`.
-
-Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
-an alternative destination. With SV however this becomes possible.
-Therefore, the fact that the dest is implicitly also a src should not
-mislead: due to the *prefix* they are different SV regs.
-
-* `rlwimi RA, RS, ...`
-* Rsrc1_EXTRA3 applies to RS as the first src
-* Rsrc2_EXTRA3 applies to RA as the secomd src
-* Rdest_EXTRA3 applies to RA to create an **independent** dest.
-
-With the addition of the EXTRA bits, the three registers
-each may be *independently* made vector or scalar, and be independently
-augmented to 7 bits in length.
+| ELWIDTH_SRC | `6:7` | Element Width for Source |
+| SUBVL | `8:9` | Sub-vector length |
+| MODE | `19:23` | changes Vector behaviour |
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-## RM-2P-1S1D/2S
+* MODE changes the behaviour of the SV operation (result saturation, mapreduce)
+* SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
+* ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
+* MASK and MASK_KIND provide predication (two types of sources: scalar INT and Vector CR).
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
-
-## RM-2P-2S1D/1S2D/3S
-
-The primary purpose for this encoding is for Twin Predication on LOAD
-and STORE operations. see [[sv/ldst]] for detailed anslysis.
-
-RM-2P-2S1D:
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
-is in bits 8:9, Rdest1_EXTRA2 in 10:11)
-
-Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
-
-Note also that LD with update indexed, which takes 2 src and 2 dest
-(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
-Twin Predication. therefore these are treated as RM-2P-2S1D and the
-src spec for RA is also used for the same RA as a dest.
+Bits 10 to 18 are further decoded depending on RM category for the instruction.
+These are given designations such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
* **N** sets signed/unsigned saturation.
**RC1** as if Rc=1, stores CRs *but not the result*
-# R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
-
-EXTRA is the means by which two things are achieved:
-
-1. Registers are marked as either Vector *or Scalar*
-2. Register field numbers (limited typically to 5 bit)
- are extended in range, both for Scalar and Vector.
-
-In the following tables register numbers are constructed from the
-standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
-interoperability between prefixing and nonprefixing of scalar registers
-is direct and convenient (when the EXTRA field is all zeros).
-
-A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
-
- if extra3_mode:
- spec = EXTRA3
- else:
- spec = EXTRA2 << 1 # same as EXTRA3, shifted
- if spec[2]: # vector
- return (RA << 2) | spec[0:1]
- else: # scalar
- return (spec[0:1] << 5) | RA
-
-## INT/FP EXTRA3
-
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming). also, these are the
-encodings used in the original SV Prefix scheme. the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
-
-| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
-|-----------|-------|---------------|---------------------|
-| 000 | Scalar | `r0-r31` | `0b00 RA` |
-| 001 | Scalar | `r32-r63` | `0b01 RA` |
-| 010 | Scalar | `r64-r95` | `0b10 RA` |
-| 011 | Scalar | `r96-r127` | `0b11 RA` |
-| 100 | Vector | `r0-r124` | `RA 0b00` |
-| 101 | Vector | `r1-r125` | `RA 0b01` |
-| 110 | Vector | `r2-r126` | `RA 0b10` |
-| 111 | Vector | `r3-r127` | `RA 0b11` |
-
-## INT/FP EXTRA2
-
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
-
-| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
-|-----------|-------|---------------|---------------------|
-| 00 | Scalar | `r0-r31` | `0b00 RA` |
-| 01 | Scalar | `r32-r63` | `0b01 RA` |
-| 10 | Vector | `r0-r124` | `RA 0b00` |
-| 11 | Vector | `r2-r126` | `RA 0b10` |
-
-## CR EXTRA3
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
- Encoding shown MSB down to LSB
-
-| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|------|---------| --------|---------|
-| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
-| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
-| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
-| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
-
-## CR EXTRA2
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
-Encoding shown MSB down to LSB
-
-| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|--------|---------|---------|---------|
-| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-
# ELWIDTH Encoding
Default behaviour is set to 0b00 so that zeros follow the convention of
`offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
+# Extra Remapped Encoding
+
+Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants.
+
+There are two categories: Single and Twin Predication.
+Due to space considerations further subdivision of Single Predication
+is based on whether the number of src operands is 2 or 3. The full list of which instructions use which remaps is here [[opcode_regs_deduped]].
+
+* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
+* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
+* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
+* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
+* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
+
+## RM-1P-3S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
+| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
+| reserved | `18` | reserved |
+
+## RM-1P-2S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|-------------------------------------------|
+| Rdest\_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
+| Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
+
+These are for 2 operand 1 dest instructions, such as `add RT, RA,
+RB`. However also included are unusual instructions with an implicit dest
+that is identical to its src reg, such as `rlwinmi`.
+
+Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
+an alternative destination. With SV however this becomes possible.
+Therefore, the fact that the dest is implicitly also a src should not
+mislead: due to the *prefix* they are different SV regs.
+
+* `rlwimi RA, RS, ...`
+* Rsrc1_EXTRA3 applies to RS as the first src
+* Rsrc2_EXTRA3 applies to RA as the secomd src
+* Rdest_EXTRA3 applies to RA to create an **independent** dest.
+
+With the addition of the EXTRA bits, the three registers
+each may be *independently* made vector or scalar, and be independently
+augmented to 7 bits in length.
+
+## RM-2P-1S1D/2S
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
+| MASK_SRC | `16:18` | Execution Mask for Source |
+
+`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+
+## RM-2P-2S1D/1S2D/3S
+
+The primary purpose for this encoding is for Twin Predication on LOAD
+and STORE operations. see [[sv/ldst]] for detailed anslysis.
+
+RM-2P-2S1D:
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2_EXTRA2 | `14:16` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| MASK_SRC | `17:18` | Execution Mask for Source |
+
+Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
+is in bits 10:11, Rdest1_EXTRA2 in 12:13)
+
+Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
+
+Note also that LD with update indexed, which takes 2 src and 2 dest
+(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
+Twin Predication. therefore these are treated as RM-2P-2S1D and the
+src spec for RA is also used for the same RA as a dest.
+
+Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
+
+# R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
+
+EXTRA is the means by which two things are achieved:
+
+1. Registers are marked as either Vector *or Scalar*
+2. Register field numbers (limited typically to 5 bit)
+ are extended in range, both for Scalar and Vector.
+
+In the following tables register numbers are constructed from the
+standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
+or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
+interoperability between prefixing and nonprefixing of scalar registers
+is direct and convenient (when the EXTRA field is all zeros).
+
+A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
+
+ if extra3_mode:
+ spec = EXTRA3
+ else:
+ spec = EXTRA2 << 1 # same as EXTRA3, shifted
+ if spec[2]: # vector
+ return (RA << 2) | spec[0:1]
+ else: # scalar
+ return (spec[0:1] << 5) | RA
+
+## INT/FP EXTRA3
+
+alternative which is understandable and, if EXTRA3 is zero, maps to
+"no effect" (scalar OpenPOWER ISA field naming). also, these are the
+encodings used in the original SV Prefix scheme. the reason why they
+were chosen is so that scalar registers in v3.0B and prefixed scalar
+registers have access to the same 32 registers.
+
+| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
+|-----------|-------|---------------|---------------------|
+| 000 | Scalar | `r0-r31` | `0b00 RA` |
+| 001 | Scalar | `r32-r63` | `0b01 RA` |
+| 010 | Scalar | `r64-r95` | `0b10 RA` |
+| 011 | Scalar | `r96-r127` | `0b11 RA` |
+| 100 | Vector | `r0-r124` | `RA 0b00` |
+| 101 | Vector | `r1-r125` | `RA 0b01` |
+| 110 | Vector | `r2-r126` | `RA 0b10` |
+| 111 | Vector | `r3-r127` | `RA 0b11` |
+
+## INT/FP EXTRA2
+
+alternative which is understandable and, if EXTRA2 is zero will map to
+"no effect" i.e Scalar OpenPOWER register naming:
+
+| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
+|-----------|-------|---------------|---------------------|
+| 00 | Scalar | `r0-r31` | `0b00 RA` |
+| 01 | Scalar | `r32-r63` | `0b01 RA` |
+| 10 | Vector | `r0-r124` | `RA 0b00` |
+| 11 | Vector | `r2-r126` | `RA 0b10` |
+
+## CR EXTRA3
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+
+ Encoding shown MSB down to LSB
+
+| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
+|-------------|------|---------| --------|---------|
+| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
+| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
+| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
+| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
+| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
+| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
+| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
+
+## CR EXTRA2
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+
+Encoding shown MSB down to LSB
+
+| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
+|-------------|--------|---------|---------|---------|
+| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
+| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
+| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
+| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+
+# Appendix
+
+Now at its own page: [[svp64/appendix]]
+
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