Simple-V is a type of Vectorization best described as a "Prefix Loop
Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
to the 8086 `REP`[^bib_rep] Prefix instruction. More advanced features are similar
-to the Z80 `CPIR`[^bib_cpir] instruction. If naively viewed one-dimensionally as an
-actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
-Vector instructions on the SFFS Subset and closer to 10 million 64-bit
-True-Scalable Vector instructions if introduced on VSX. SVP64, the
-instruction format used by Simple-V, is therefore best viewed as an
-orthogonal RISC-paradigm "Loop Prefixing" subsystem instead.
+to the Z80 `CPIR`[^bib_cpir] instruction.
[^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
[^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
the following instruction (also a Defined Word-instruction), but does **not** change the actual Decoding
of that following instruction just because it is Prefixed. Unlike EXT100-163,
where the Suffix is considered an entirely new Opcode Space,
-SVP64-Prefixed instructions **MUST NEVER** be treated or regarded
+SVP64-Prefixed instructions must never be treated or regarded
as a different Opcode Space.
[^dwi]: Defined Word-instruction: Power ISA v3.1 Section 1.6
-*Architectural note: Treating the SVP64 Prefix as an "Independent" 64-bit Encoding Space and attempting
-to allocate non-Orthogonal Opcodes within it will result
-in catastrophic unviability of Simple-V. The Orthogonality of the Scalar vs Prefixed-Scalar
-spaces has to be considered inviolate, to the extent that even RESERVED spaces must be
-kept identical. The complexity at the Decode Phase by violating the RISC paradigm inherent
-in Simple-V will be unimplementable*
-
Two apparent exceptions to the above hard rule exist: SV
Branch-Conditional operations and LD/ST-update "Post-Increment"
Mode. Post-Increment was considered sufficiently high priority
Therefore it has to be prohibited to accept RFCs
which fundamentally violate the following hard requirement: **under no circumstances**
must the use of SVP64 24-bit Suffixes **also** imply a different Opcode space
-from **any** non-prefixed Word, even RESERVED or Illegal Words.*
+from **any** non-prefixed Word. Even RESERVED or Illegal Words must be
+Orthogonal.*
Subset implementations in hardware are permitted, as long as certain
rules are followed, allowing for full soft-emulation including future
Different classes of operations require different formats. The earlier
sections cover the common formats and the five separate modes have their own
section later:
-CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
-Immediate, Load/Store Indexed, and Branch-Conditional.
+* CR operations (crops),
+* Arithmetic/Logical (termed "normal"),
+* Load/Store Immediate,
+* Load/Store Indexed,
+* Branch-Conditional.
## Definition of Reserved in this spec.
Simple-V operates on an entirely different paradigm from traditional
Vector ISAs: as a "Sub-Execution Context", where "Elements" are synonymous
with Scalar instructions. With this in mind
-implementations must observe Strict **Element**-Level Execution Order[^svp64_eeo]
+implementations must observe Strict **Element**-Level Execution Order[[#svp64_eeo]]
at all times.
-*Any* element is Interruptible and Architectural State may
+*Any* element is Interruptible, and Architectural State may
be fully preserved and restored regardless of that same State.
*Engineering note: implementations are permitted have higher latency to
Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
but the full SVP64 Architectural State may be saved and
restored through manual copying of `SVSTATE` (and the four
-REMAP SPRs if in use at the time)
+REMAP SPRs if in use at the time, which may be determined by
+`SVSTATE[32:46]` being non-zero).
*Programmer's note: Trap Handlers (and any stack-based context save/restore)
must avoid the use of SVP64 Prefixed instructions to perform the necessary
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