-# SVP64 for OpenPOWER ISA v3.0B
+[[!tag standards]]
-This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
+# DRAFT SVP64 for OpenPOWER ISA v3.0B
+
+* **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
+
+This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
+
+Credits and acknowledgements:
+
+* Luke Leighton
+* Jacob Lifshay
+* Hendrik Boom
+* Richard Wilbur
+* Alexandre Oliva
+* Cesar Strauss
+* NLnet Foundation, for funding
+* OpenPOWER Foundation
+* Paul Mackerras
+* Toshaan Bharvani
+* IBM for the Power ISA itself
Links:
# Introduction
-This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It is best read in conjunction with the [[sv/overview]] which explains the background.
+This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
The plan is to create an encoding for SVP64, then to create an encoding
for SVP48, then to reorganize them both to improve field overlap,
| 0:5 | 6:31 | 0:31 |
|--------|--------------|--------------|
-| EXT01 | v3.1B Prefix | v3.1B Suffix |
+| EXT01 | v3.1 Prefix | v3.1 Suffix |
-svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
+svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
## SVP64 encoding features
* Independent per-register Scalar/Vector tagging and range extension on every register
* Element width overrides on both source and destination
* Predication on both source and destination
-* Two different *types* of predication: INT and CR
-* SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
+* Two different sources of predication: INT and CR Fields
+* SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
predicate-result mode.
This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
fields set to a reserved value must cause an illegal instruction trap,
to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
-This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
+This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
+is intended the red keyword `RESERVED` is used.
# Identity Behaviour
Where the integer regfile in standard scalar
OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
-extended to 64 entries, CR0 thru CR63.
+extended to 128 entries, CR0 thru CR127.
The names of the registers therefore reflects a simple linear extension
of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
| EXT01 | RM | 1 | RM | 1 | RM |
| 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
-Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
+Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
instruction. That instruction becomes "prefixed" with the SVP context: the
Remapped Encoding field (RM).
+It is important to note that unlike v3.1 64-bit prefixed instructions
+there is insufficient space in `RM` to provide identification of
+any SVP64 Fields without first partially decoding the
+32-bit suffix. Extreme caution and care must therefore be taken
+when extending SVP64 in future, to not create unnecessary relationships
+between prefix and suffix that could complicate decoding, adding latency.
+
# Common RM fields
The following fields are common to all Remapped Encodings:
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
-| MASKMODE | `0` | Execution (predication) Mask Kind |
-| MASK | `1:3` | Execution Mask |
+| MASKMODE | `0` | Execution (predication) Mask Kind |
+| MASK | `1:3` | Execution Mask |
+| SUBVL | `8:9` | Sub-vector length |
+
+The following fields are optional or encoded differently depending
+on context after decoding of the Scalar suffix:
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
| ELWIDTH | `4:5` | Element Width |
| ELWIDTH_SRC | `6:7` | Element Width for Source |
-| SUBVL | `8:9` | Sub-vector length |
+| EXTRA | `10:18` | Register Extra encoding |
| MODE | `19:23` | changes Vector behaviour |
+
* MODE changes the behaviour of the SV operation (result saturation, mapreduce)
* SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
* ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
* MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
+* Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
-Bits 10 to 18 are further decoded depending on RM category for the instruction.
Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
# Mode
-Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
-
-These are the modes:
+Mode is an augmentation of SV behaviour. Different types of
+instructions have different needs, similar to Power ISA
+v3.1 64 bit prefix 8LS and MTRR formats apply to different
+instruction types. Modes include Reduction, Iteration, arithmetic
+saturation, and Fail-First. More specific details in each
+section and in the [[svp64/appendix]]
-* **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results.
-* **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
- *VL is altered as a result*.
-* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping.
-* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]]
- note that there are comprehensive caveats when using this mode.
-* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
-
-Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
-
-The Mode table is laid out as follows:
-
-| 0-1 | 2 | 3 4 | description |
-| --- | --- |---------|-------------------------- |
-| 00 | 0 | sz dz | normal mode |
-| 00 | 1 | sz CRM | reduce mode (mapreduce), SUBVL=1 |
-| 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 |
-| 01 | inv | CR-bit | Rc=1: ffirst CR sel |
-| 01 | inv | sz RC1 | Rc=0: ffirst z/nonz |
-| 10 | N | sz dz | sat mode: N=0/1 u/s |
-| 11 | inv | CR-bit | Rc=1: pred-result CR sel |
-| 11 | inv | sz RC1 | Rc=0: pred-result z/nonz |
-
-Fields:
-
-* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context.
-* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
-* **CRM** affects the CR on reduce mode when Rc=1
-* **SVM** sets "subvector" reduce mode
-* **N** sets signed/unsigned saturation.
-**RC1** as if Rc=1, stores CRs *but not the result*
-
-## LD/ST ffirst
-
-ffirst LD/ST to multiple pages via a Vectorised base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore in these special circumstances requesting ffirst eith a vector base is instead interpreted as element-strided LD/ST. See <https://bugs.libre-soc.org/show_bug.cgi?id=561>
+* For condition register operations see [[sv/cr_ops]]
+* For LD/ST Modes, see [[sv/ldst]].
+* For Branch modes, see [[sv/branches]]
+* For arithmetic and logical, see [[sv/normal]]
# ELWIDTH Encoding
[`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
is reserved for a future implementation of SV
-## Elwidth for CRs:
-
-TODO, important, particularly for crops, mfcr and mtcr, what elwidth
-even means. instead it may be possible to use the bits as extra indices
-(add to EXTRA2/3) to access the full 64 CRs at the bit level. TBD, several ideas
-
-The actual width of the CRs cannot be altered: they are 4 bit. Also,
-for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
-the INT/FP result to which the elwidth override applies, *not* the CR.
-This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
+Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
+perform its operation at **half** the ELWIDTH then padded back out
+to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
+clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
+then padded back out to fit in IEEE754 FP64, exactly as for Scalar
+v3.0B "single" FP.
-As mentioned TBD, this leaves crops etc. to have a meaning defined for
-elwidth, because these ops are pure explicit CR based.
+## Elwidth for CRs:
-Examples: mfxm may take the extra bits and use them as extra mask bits.
+Element-width overrides for CR Fields has no meaning. The bits
+are therefore used for other purposes, or when Rc=1, the Elwidth
+applies to the result being tested, but not to the Vector of CR Fields.
-Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
# SUBVL Encoding
Likewise CR based twin predication has a second set of 3 bits, allowing
a different test to be applied.
+Note that it is assumed that Predicate Masks (whether INT or CR)
+are read *before* the operations proceed. In practice (for CR Fields)
+this creates an unnecessary block on parallelism. Therefore,
+it is up to the programmer to ensure that the CR fields used as
+Predicate Masks are not being written to by any parallel Vector Loop.
+Doing so results in **UNDEFINED** behaviour, according to the definition
+outlined in the OpenPOWER v3.0B Specification.
+
+Hardware Implementations are therefore free and clear to delay reading
+of individual CR fields until the actual predicated element operation
+needs to take place, safe in the knowledge that no programmer will
+have issued a Vector Instruction where previous elements could have
+overwritten (destroyed) not-yet-executed CR-Predicated element operations.
+
## Integer Predication (MASKMODE=0)
When the predicate mode bit is zero the 3 bits are interpreted as below.
| 110 | R30 | `R30 & (1 << i)` is non-zero |
| 111 | ~R30 | `R30 & (1 << i)` is zero |
+r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
+
## CR-based Predication (MASKMODE=1)
When the predicate mode bit is one the 3 bits are interpreted as below.
`offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
+Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
+
# Extra Remapped Encoding
-Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
+Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
+
+These mappings are part of the SVP64 Specification in exactly the same
+way as X-Form, D-Form. New Scalar instructions added to the Power ISA
+will need a corresponding SVP64 Mapping, which can be derived by-rote
+from examining the Register "Profile" of the instruction.
There are two categories: Single and Twin Predication.
Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
+is based on whether the number of src operands is 2 or 3. With only
+9 bits available some compromises have to be made.
* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+## RM-1P-2S1D
+
+single-predicate, three registers (2 read, 1 write)
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `10:12` | extends Rdest |
+| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
+| Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
+
## RM-2P-2S1D/1S2D/3S
The primary purpose for this encoding is for Twin Predication on LOAD
2. Register field numbers (limited typically to 5 bit)
are extended in range, both for Scalar and Vector.
+The register files are therefore extended:
+
+* INT is extended from r0-31 to 128
+* FP is extended from fp0-32 to 128
+* CR is extended from CR0-7 to CR0-127
+
In the following tables register numbers are constructed from the
standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
spec = EXTRA3
else:
spec = EXTRA2 << 1 # same as EXTRA3, shifted
- if spec[2]: # vector
- return (RA << 2) | spec[0:1]
+ if spec[0]: # vector
+ return (RA << 2) | spec[1:2]
else: # scalar
- return (spec[0:1] << 5) | RA
+ return (spec[1:2] << 5) | RA
+
+Future versions may extend to 256 by shifting Vector numbering up.
+Scalar will not be altered.
## INT/FP EXTRA3
were chosen is so that scalar registers in v3.0B and prefixed scalar
registers have access to the same 32 registers.
-| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
+Fields are as follows:
+
+* Value: R_EXTRA3
+* Mode: register is tagged as scalar or vector
+* Range/Inc: the range of registers accessible from this EXTRA
+ encoding, and the "increment" (accessibility). "/4" means
+ that this EXTRA encoding may only give access (starting point)
+ every 4th register.
+* MSB..LSB: the bit field showing how the register opcode field
+ combines with EXTRA to give (extend) the register number (GPR)
+
+| Value | Mode | Range/Inc | 6..0 |
|-----------|-------|---------------|---------------------|
-| 000 | Scalar | `r0-r31` | `0b00 RA` |
-| 001 | Scalar | `r32-r63` | `0b01 RA` |
-| 010 | Scalar | `r64-r95` | `0b10 RA` |
-| 011 | Scalar | `r96-r127` | `0b11 RA` |
-| 100 | Vector | `r0-r124` | `RA 0b00` |
-| 101 | Vector | `r1-r125` | `RA 0b01` |
-| 110 | Vector | `r2-r126` | `RA 0b10` |
-| 111 | Vector | `r3-r127` | `RA 0b11` |
+| 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
+| 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
+| 100 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 101 | Vector | `r1-r125`/4 | `RA 0b01` |
+| 110 | Vector | `r2-r126`/4 | `RA 0b10` |
+| 111 | Vector | `r3-r127`/4 | `RA 0b11` |
## INT/FP EXTRA2
alternative which is understandable and, if EXTRA2 is zero will map to
"no effect" i.e Scalar OpenPOWER register naming:
-| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
-|-----------|-------|---------------|---------------------|
-| 00 | Scalar | `r0-r31` | `0b00 RA` |
-| 01 | Scalar | `r32-r63` | `0b01 RA` |
-| 10 | Vector | `r0-r124` | `RA 0b00` |
-| 11 | Vector | `r2-r126` | `RA 0b10` |
+| Value | Mode | Range/inc | 6..0 |
+|-----------|-------|---------------|-----------|
+| 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
+| 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
+| 10 | Vector | `r0-r124`/4 | `RA 0b00` |
+| 11 | Vector | `r2-r126`/4 | `RA 0b10` |
## CR EXTRA3
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
Encoding shown MSB down to LSB
-| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|------|---------| --------|---------|
-| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
-| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
-| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
-| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|------|---------------|-----------| --------|---------|
+| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
+| 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
+| 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
+| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
+| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
## CR EXTRA2
Encoding shown MSB down to LSB
-| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|--------|---------|---------|---------|
-| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+| Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
+|-------|--------|----------------|---------|---------|---------|
+| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
+| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
+| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
+| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
# Appendix
projects / libreriscv.git / blobdiff