* 1: select INT or CR predication
* 3: predicate selection and inversion (QTY 2 for tpred)
* 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
-* 2: saturate mode
+* 3: saturate mode
-totals: 24 bits (dest elwidth shared)
+totals: 22 bits (dest elwidth shared)
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
* ptyp - predication INT / CR
* psrc / pdst - predicate mask selector and inversion
* vspec - 3 bit src / dest scalar-vector extension
-* sat: 0bSU - S=1 signed U=1 unsigned 0b11 reserved
+* sat: 2 bit s/u
## twin predication, CR based.
* ptyp - predication INT / CR
* pred - predicate mask selector and inversion
* vspec - 2/3 bit src / dest scalar-vector extension
-* sat: 0bSU - S=1 signed U=1 unsigned 0b11 reserved
+* sat: 2 bit s/u
+
For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits.
Note:
-* saturation is done on the result at the **source** elwidth
-* signed-saturation causes sign-extension from source to dest elwidths **after** saturation
+* for saturation the operation is done at the **source** width
+ (this is different from normal elwidth overrides which
+ are done at the **dest** width)
+* saturation is done on the result at the **dest** elwidth
# Notes about rounding, clamp and saturate
If there are spare bits it would be very good to look at using some of them to specify the mode, because otherwise a SPR has to be used which will need to be set and unset. This can get costly.
-Idea: 2 bits for clamping mode? similar to elwidth:
-
-
-
-* 0b00 default (no clamp)
-* 0b01 8 bit (sel: -128/127, us:0/255)
-* 0b10 16 bit
-* 0b11 32 bit
-
-not the same *as* elwidth.
-
# Notes about Swizzle
Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.