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[libreriscv.git] / openpower / sv / tern_bin.mdwn

diff --git a/openpower/sv/tern_bin.mdwn b/openpower/sv/tern_bin.mdwn
index e8bcafcb420feae8837079fe446f03d79208df88..d1fb67448f92f1638b856ba3653661dd890a611e 100644 (file)
--- a/openpower/sv/tern_bin.mdwn
+++ b/openpower/sv/tern_bin.mdwn
@@ -4,13 +4,13 @@ Add this section to Book I 3.3.13
 
 TLI-form
 
-* `ternlogi RT, RA, RB, TLI` (`Rc=0`)
-* `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
-
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form     |
 |-----|------|-------|-------|-------|-------|----|----------|
 | PO  | RT   |  RA   |  RB   | TLI   | XO    | Rc | TLI-Form |
 
+* `ternlogi RT, RA, RB, TLI` (`Rc=0`)
+* `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
+
 Pseudocode:
 
 ```
@@ -37,7 +37,10 @@ For each integer value i, 0 to 63, do the following.
     evaluated by this instruction for any given value of TLI.
 ```
 
-*Programmer's Note: this is a Read-Modify-Write instruction on RT.*
+*Programmer's Note: this is a Read-Modify-Write instruction on RT.
+A simple copy instruction may be used to achieve the effect of
+3-in 1-out. The copy instruction should come immediately before
+`ternlogi` so that hardware may optionally Macro-Op Fuse them*
 
 *Programmer's note: This instruction is useful when combined with Matrix REMAP
 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
@@ -59,12 +62,12 @@ Add this section to Book I 2.5.1
 
 CRB-form
 
-* `crternlogi BF, BFA, BFB, BFC, TLI, msk`
-
 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form     |
 |----|----|----|-----|-----|-----|-----|-----|---|----------|
 | PO | BF | msk|BFA  | msk | BFB | TLI | XO  |TLI| CRB-Form |
 
+* `crternlogi BF, BFA, BFB, BFC, TLI, msk`
+
 Pseudocode:
 
 ```
@@ -107,7 +110,10 @@ If `msk` is zero an Illegal Instruction trap is raised.
 *Programmer's Note: this instruction is a "masked" overwrite on CR Field
 BF. For each bit set in msk a Write is performed but for each bit clear
 in msk the corresponding bit of BF is preserved. Overall this makes
-crbinlog a conditionally Read-Modify-Write instruction on CR Field BF*
+crbinlog a conditionally Read-Modify-Write instruction on CR Field BF.
+A simple copy instruction may be used to achieve the effect of
+3-in 1-out. The copy instruction should come immediately before
+`crternlogi` so that hardware may optionally Macro-Op Fuse them*
 
 Special registers altered:
 
@@ -125,12 +131,12 @@ Add this section to Book I 3.3.13
 
 VA-form
 
-* `binlog RT, RA, RB, RC, nh`
-
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form    |
 |-----|------|-------|-------|-------|----|-------|---------|
 | PO  |  RT  |  RA   |  RB   |  RC   | nh | XO    | VA-Form |
 
+* `binlog RT, RA, RB, RC, nh`
+
 Pseudocode:
 
 ```
@@ -193,6 +199,8 @@ CRB-form
 |----|----|----|-----|-----|-----|-----|-----|---|----------|
 | PO | BF | msk|BFA  | msk | BFB | //  | XO  |// | CRB-Form |
 
+* `crbinlog BF, BFA, BFB, msk`
+
 Pseudocode:
 
 ```
@@ -238,7 +246,10 @@ Special registers altered:
 Field BF. For each bit set in `msk` a Write is performed
 but for each bit clear in `msk` the corresponding bit of BF is
 preserved. Overall this makes `crbinlog` a conditionally
-Read-Modify-Write instruction on CR Field BF*
+Read-Modify-Write instruction on CR Field BF.
+A simple copy instruction may be used to achieve the effect of
+3-in 1-out. The copy instruction should come immediately before
+`crternlogi` so that hardware may optionally Macro-Op Fuse them*
 
 [[!tag standards]]