(no commit message)

[libreriscv.git] / openpower / sv / toc_data_pointer.mdwn

diff --git a/openpower/sv/toc_data_pointer.mdwn b/openpower/sv/toc_data_pointer.mdwn
index c868d50e7caa314070554cb275a5f66b1ecd2242..74b1c9d1f2162463593ce7e0b458474039ccc361 100644 (file)
--- a/openpower/sv/toc_data_pointer.mdwn
+++ b/openpower/sv/toc_data_pointer.mdwn
@@ -26,7 +26,13 @@ Behind the scenes, the first ld (estsblishing the entry pointed to via the TOC)
 
 What instead if this could be replaced by:
 
-    cmpli r5, {TOC+8}
+    cmpi r5, {TOC+8}
 
 where again, behind the scenes, a hidden micro-coded LD occurs at an address 8(TOC) to be loaded into the immediate operand, as if it were possible to have a full 64 bit operand in the cmpli instruction?
 
+This could hypothetically be encoded with existing v3.0B instructions, loading the 64 bit immediate into a temporary register, followed by using cmp rather than cmpi:
+
+    ld r9, 8(r10) # r10 loaded from TOC
+    cmp r5, r9
+
+However the very fact that it requires the extra LD instruction (explicitly, rather than implicitly micro-coded) tells us that there is still a benefit to this approach.  Additionally: one less GPR is required.