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[libreriscv.git] / openpower / sv / toc_data_pointer.mdwn

diff --git a/openpower/sv/toc_data_pointer.mdwn b/openpower/sv/toc_data_pointer.mdwn
index 3342754cb4abf7af818708ac3328a467deeb97fb..74b1c9d1f2162463593ce7e0b458474039ccc361 100644 (file)
--- a/openpower/sv/toc_data_pointer.mdwn
+++ b/openpower/sv/toc_data_pointer.mdwn
@@ -15,4 +15,24 @@ The first three instructions are setup to establish the desired address with the
 
     lwz r9, {TOC+4}(r0)
 
-Behind the scenes, 
+Behind the scenes, the first ld (estsblishing the entry pointed to via the TOC) occurs automatically.  However this is only one instruction saved.  What if large immediates were stored at data pointed to via the TOC, as well? Take the following code (a common pattern for 64 bit immediates):
+
+    addi r9, r0, NNNN
+    addis r9, r9, NNNN
+    sldi r9, r9, 32
+    addi r9, r9, NNNN
+    addis r9, r9, NNNN
+    cmpl r5, r9 # actual operation, test r5
+
+What instead if this could be replaced by:
+
+    cmpi r5, {TOC+8}
+
+where again, behind the scenes, a hidden micro-coded LD occurs at an address 8(TOC) to be loaded into the immediate operand, as if it were possible to have a full 64 bit operand in the cmpli instruction?
+
+This could hypothetically be encoded with existing v3.0B instructions, loading the 64 bit immediate into a temporary register, followed by using cmp rather than cmpi:
+
+    ld r9, 8(r10) # r10 loaded from TOC
+    cmp r5, r9
+
+However the very fact that it requires the extra LD instruction (explicitly, rather than implicitly micro-coded) tells us that there is still a benefit to this approach.  Additionally: one less GPR is required.