add ls001.po9 RFC

[libreriscv.git] / openpower / sv / twin_butterfly.mdwn

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index c2014930b3392527225e61ffc5336006157d352e..32a968914925f0a0579e364fd411f83b40b47ec7 100644 (file)
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -4,7 +4,7 @@
 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD>
 * [[openpower/isa/svfparith]]
 
-# [DRAFT] Twin Butterfly DCT Instruction(s)
+# Twin Butterfly Integer DCT Instruction(s)
 
 The goal is to implement instructions that calculate the expression:
 
@@ -32,7 +32,7 @@ Arm includes special instructions to optimize these operations, although they ar
 The suggestion is to have a single instruction to calculate both values `((a + b) * c) >> N`, and `((a - b) * c) >> N`.
 The instruction will run in accumulate mode, so in order to calculate the 2-coeff version one would just have to call the same instruction with different order a, b and a different constant c.
 
-# [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
+## [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
 
 A-Form
 
@@ -49,12 +49,14 @@ Pseudo-code:
     res1 <- ROTL64(prod1, XLEN-n)
     res2 <- ROTL64(prod2, XLEN-n)
     m <- MASK(n, (XLEN-1))
-    s1 <- res1[0]
-    s2 <- res2[0]
-    smask1 <- ([s1]*XLEN) & ¬m
-    smask2 <- ([s2]*XLEN) & ¬m
-    RT <- res1 & m | smask1
-    RS <- res2 & m | smask2
+    signbit1 <- res1[0]
+    signbit2 <- res2[0]
+    smask1 <- ([signbit1]*XLEN) & ¬m
+    smask2 <- ([signbit2]*XLEN) & ¬m
+    s64_1 <- [0]*(XLEN-1) || signbit1
+    s64_2 <- [0]*(XLEN-1) || signbit2
+    RT <- (res1 & m | smask1) + s64_1
+    RS <- (res2 & m | smask2) + s64_2
 ```
 
 Special Registers Altered:
@@ -68,7 +70,6 @@ Where we have added this variant in A-Form (defined in fields.txt):
 ```
 # # 1.6.17 A-FORM
     |0     |6     |11      |16     |21      |26    |31 |
-    ...
     | PO   |  RT  |   RA   |   RB  |   SH   |   XO |Rc |
 
 ```
@@ -80,13 +81,15 @@ The instruction has been added to `minor_22.csv`:
 ```
 
 
-# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+# Twin Butterfly Integer DCT Instruction(s)
 
-DCT-Form
+## [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+X-Form
 
 ```
-    |0     |6     |11      |16     |21      |26    |31 |
-    | PO   |  FRT |   FRA  |   FRB |   //   |   XO |Rc |
+    |0     |6     |11      |16     |21      |31 |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   | Rc|
 ```
 
 * fdmadds FRT,FRA,FRB (Rc=0)
@@ -108,3 +111,31 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 ```
+
+## [DRAFT] Floating Multiply-Add FFT [Single]
+
+X-Form
+
+```
+    |0     |6     |11      |16     |21      |31 |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   | Rc|
+```
+
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRS <- FPMULADD32(FRT, FRA, FRB, -1, 1)
+    FRT <- FPMULADD32(FRT, FRA, FRB, 1, 1)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+```