* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD>
* [[openpower/isa/svfparith]]
-# [DRAFT] Twin Butterfly DCT Instruction(s)
+# Twin Butterfly Integer DCT Instruction(s)
The goal is to implement instructions that calculate the expression:
The suggestion is to have a single instruction to calculate both values `((a + b) * c) >> N`, and `((a - b) * c) >> N`.
The instruction will run in accumulate mode, so in order to calculate the 2-coeff version one would just have to call the same instruction with different order a, b and a different constant c.
-# [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
+## [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
A-Form
```
# # 1.6.17 A-FORM
|0 |6 |11 |16 |21 |26 |31 |
- ...
| PO | RT | RA | RB | SH | XO |Rc |
```
```
-# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+# Twin Butterfly Integer DCT Instruction(s)
-DCT-Form
+## [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+X-Form
```
- |0 |6 |11 |16 |21 |26 |31 |
- | PO | FRT | FRA | FRB | // | XO |Rc |
+ |0 |6 |11 |16 |21 |31 |
+ | PO | FRT | FRA | FRB | XO | Rc|
```
* fdmadds FRT,FRA,FRB (Rc=0)
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
```
+
+## [DRAFT] Floating Multiply-Add FFT [Single]
+
+X-Form
+
+```
+ |0 |6 |11 |16 |21 |31 |
+ | PO | FRT | FRA | FRB | XO | Rc|
+```
+
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+ FRS <- FPMULADD32(FRT, FRA, FRB, -1, 1)
+ FRT <- FPMULADD32(FRT, FRA, FRB, 1, 1)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+ CR1 (if Rc=1)
+```