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[libreriscv.git] / openpower / sv / vector_isa_comparison.mdwn

diff --git a/openpower/sv/vector_isa_comparison.mdwn b/openpower/sv/vector_isa_comparison.mdwn
index 55e28b2fcfed414e7ac2616adeeff375804f739c..b8c51490c8ac124ecc1042200eaf56680965bf2f 100644 (file)
--- a/openpower/sv/vector_isa_comparison.mdwn
+++ b/openpower/sv/vector_isa_comparison.mdwn
@@ -55,12 +55,16 @@ of a Vector Processor. Transcendentals can be added as a sub-RFC.
 
 There is considerable confusion surrounding Vector ISAs
 because of a mis-use of the word "Vector" in the marketing
-material of most well-known Packed SIMD ISAs. These Packed
+material of most well-known Packed SIMD ISAs of the past 3
+decades. These Packed
 SIMD ISAs used features "inspired" from Scalable Vector ISAs.
 
 * PackedSIMD VSX. VSX, which has the word "Vector" in its name,
   is "inspired" by Vector Processing
   but has no "Scaling" capability, and no Predicate masking.
+  Both these factors put pressure on developers to use
+  "inline assembler unrolling" and data repetition, which in turn
+  is detrimental to both L1 Data and Instruction Caches.
   Adding Predicate Masks to the PackedSIMD VSX ISA
   would effectively double the number of PackedSIMD
   instructions (750 becomes 1,500) even if it were practical
@@ -72,8 +76,11 @@ SIMD ISAs used features "inspired" from Scalable Vector ISAs.
   in AVX-512.
 * ARM NEON - accurately described as a Packed SIMD ISA in
   all literature.
-* ARM SVE / SVE2 - partially accurately described as a Scalable Vector
-  ISA, but the "Scaling" is, rather unfortunately, a parameter
+* ARM SVE / SVE2 - **not a Scalable Vector ISA**, it is actually
+  a hybrid PackedSIMD/PredicatedSIMD ISA: with 4-operand instructions
+  being overwrite to fit into 32-bit there was no room for a predicate
+  mask.
+  The "Scaling" is, rather unfortunately, a parameter
   that is chosen by the *Hardware Architect*, rather than
   the programmer. The actual "Scalar" part as far as the programmer
   is concerned is supposed to be the Predicate Masks.  However in
@@ -85,16 +92,24 @@ SIMD ISAs used features "inspired" from Scalable Vector ISAs.
   going directly against the advice given on ARM's developer
   documentation.
 
+A good analogy explaining why "Silicon-Partner Scalability" is
+catastrophic is to note that the situation is near-identical to when IBM
+extended Power ISA from 32 to 64-bit.  Existing 32-bit systems
+were **unable** to run or trap-and-emulate 64-bit instructions
+**because they were the exact same opcodes** and the "Silicon Scalability"
+of both RVV and ARM SVE/2 is the exact same mistake, but much
+worse.  At least IBM provided an `MSR.SF` bit.
+
 The saving grace of PackedSIMD VSX is that it did not fall to the
 seduction outlined in the "SIMD Considered Harmful" article
 <https://www.sigarch.org/simd-instructions-considered-harmful/>.
 It is clear that it is expected to deploy Multi-Issue to achieve
-high performance, which is a much cleaner approach that does not
-result in ISA poisoning such as that suffered by x86 (AVX).
+high performance, which is a much cleaner approach that has not
+resulted in ISA poisoning such as that suffered by x86 (AVX).
 
 # Actual 3D GPU Architectures and ISAs (all SIMD)
 
-All of these are not Vector ISAs, they are SIMD ISAs.
+All of these are not Scalable Vector ISAs, they are SIMD ISAs.
 
 * Broadcom Videocore
   <https://github.com/hermanhermitage/videocoreiv>
@@ -111,7 +126,6 @@ All of these are not Vector ISAs, they are SIMD ISAs.
   implement a subset of the AMDGPU ISA (Southern Islands), aka a "GPGPU"
   <https://miaowgpu.org/>
 
-
 # Actual Scalar Vector Processor Architectures and ISAs
 
 * NEC SX Aurora
@@ -123,9 +137,21 @@ All of these are not Vector ISAs, they are SIMD ISAs.
 * MRISC32 ISA Manual (under active development)
   <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
 * Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
-  Mitch on direct contact with him.  It is a different approach from the
+  Mitch under NDA
+  on direct contact with him.  It is a different approach from the
   others, which may be termed "Cray-Style Horizontal-First" Vectorisation.
-  66000 is a *Vertical-First* Vector ISA.
+  66000 is a *Vertical-First* Vector ISA with hardware-level
+  auto-vectorisation.
+* [ETA-10](http://50.204.185.175/collections/catalog/102641713)
+  an extremely rare Scalable Vector Architecture from 1986,
+  similar to the CDC Cyber 205.
+  Only 25 machines were ever delivered. Page 3-220 of its ISA
+  shows that it had Predicate Masks and Horizontal Reduction.
+  Appendix H-1 shows it is likely a Memory-to-Memory Vector
+  Architecture, and overcame the penalties normally associated
+  with this by adding an explicit "Vector operand forwarding/chaining"
+  instruction (Page 3-69).  It is however clearly Scalable, up to Vector
+  elements of 2^16.
 
 The term Horizontal or Vertical alludes to the Matrix "Row-First" or
 "Column-First" technique, where:
@@ -146,3 +172,5 @@ Vector-type Support by Architecture
 | RVV          | X          |  |
 | SVP64        | X          | X  |
 
+![Horizontal vs Vertical](/openpower/sv/sv_horizontal_vs_vertical.svg)
+