# SV Vector Operations.
+TODO merge old standards page [[simple_v_extension/vector_ops/]]
+
The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
Notes:
* <https://i.stack.imgur.com/QSLKY.png>
* <https://stackoverflow.com/questions/27971757/big-integer-addition-code>
`((P|G)+G)^P`
+* <https://en.m.wikipedia.org/wiki/Carry-lookahead_adder>
+
+```
+ P = (A | B) & Ci
+ G = (A & B)
+```
+
+Stackoverflow algorithm `((P|G)+G)^P` works on the cumulated bits of P and G from associated vector units (P and G are integers here). The result of the algorithm is the new carry-in which already includes ripple, one bit of carry per element.
+
+```
+ At each id, compute C[id] = A[id]+B[id]+0
+ Get G[id] = C[id] > radix -1
+ Get P[id] = C[id] == radix-1
+ Join all P[id] together, likewise G[id]
+ Compute newC = ((P|G)+G)^P
+ result[id] = (C[id] + newC[id]) % radix
+```
two versions: scalar int version and CR based version.