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[libreriscv.git] / openpower / sv / vector_ops.mdwn

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index b239001b2e9f3b45bc3b0e34ebb04e2b5ca51568..67d95d4df20321619aff964b3f168ec178f47e84 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -1,6 +1,6 @@
 [[!tag standards]]
 
-# SV Vector Operations.
+# SV Vector-assist Operations.
 
 Links:
 
@@ -20,7 +20,8 @@ Therefore there are not that many cases where *actual* Vector
 instructions are needed. If they are, they are more "assistance"
 functions.  Two traditional Vector instructions were initially
 considered (conflictd and vmiota) however they may be synthesised
-from existing SVP64 instructions: details in [[discussion]]
+from existing SVP64 instructions: vmiota may use [[svstep]].
+Details in [[discussion]]
 
 Notes:
 
@@ -29,11 +30,50 @@ Notes:
 
 # Mask-suited Bitmanipulation
 
-UNDER DEVELOPMENT, sbf/sof/sif moved to [[discussion] and
-general-purpose replacements being designed
+Based on RVV masked set-before-first, set-after-first etc.
+and Intel and AMD Bitmanip instructions made generalised then
+advanced further to include masks, this is a single instruction
+covering 24 individual instructions in other ISAs.
+*(sbf/sof/sif moved to [[discussion]])*
+
+BM2-Form
+
+|0..5  |6..10|11..15|16..20|21-25|26|27..31| Form |
+|------|-----|------|------|-----|--|------|------|
+| PO   |  RS |   RA |   RB |bm   |L |   XO | BM2-Form |
+
+* bmask RS,RA,RB,bm,L
+
+The patterns within the pseudocode for AMD TBM and x86 BMI1 are
+as follows:
+
+* first pattern A: two options `x` or `~x`
+* second pattern B: three options `|` `&` or `^`
+* third pattern C: four options `x+1`, `x-1`, `~(x+1)` or `(~x)+1`
+
+Thus it makes sense to create a single instruction
+that covers all of these.  A crucial addition that is essential
+for Scalable Vector usage as Predicate Masks, is the second mask parameter
+(RB).  The additional paramater, L, if set, will leave bits of RA masked
+by RB unaltered, otherwise those bits are set to zero. Note that when `RB=0`
+then instead of reading from the register file the mask is set to all ones.
+
+The lower two bits of `bm` set to 0b11 are `RESERVED`. An illegal instruction
+trap must be raised.
+
+Executable pseudocode demo:
+
+```
+[[!inline pages="openpower/sv/bmask.py" quick="yes" raw="yes" ]]
+```
 
 # Carry-lookahead
 
+As a single scalar 32-bit instruction, up to 64 carry-propagation bits
+may be computed.  When the output is then used as a Predicate mask it can
+be used to selectively perform the "add carry" of biginteger math, with
+`sv.addi/sm=rN RT.v, RA.v, 1`.
+
 * cprop RT,RA,RB
 * cprop. RT,RA,RB