more notes about scalar reduction

[libreriscv.git] / openpower / sv / vector_ops.mdwn

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index e3603e8b4cc1f23d278f03f3a710c4c5cc1de176..d9e401db7684cc6c9c0ef9f829cb48b774c49394 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV Vector Operations.
 
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
@@ -254,9 +256,21 @@ Pseudo-code:
 
 # Carry-lookahead
 
+used not just for carry lookahead, also a special type of predication mask operation.
+
 * <https://www.geeksforgeeks.org/carry-look-ahead-adder/>
 * <https://media.geeksforgeeks.org/wp-content/uploads/digital_Logic6.png>
 * <https://electronics.stackexchange.com/questions/20085/whats-the-difference-with-carry-look-ahead-generator-block-carry-look-ahead-ge>
 * <https://i.stack.imgur.com/QSLKY.png>
 * <https://stackoverflow.com/questions/27971757/big-integer-addition-code>
   `((P|G)+G)^P`
+
+two versions: scalar int version and CR based version.
+
+scalar int version acts as a scalar carry-propagate, reading XER.CA as input, P and G as regs, and taking a radix argument.  the end bits go into XER.CA and CR0.ge
+
+vector version takes CR0.so as carry in, stores in CR0.so and CR.ge end bits.
+
+if zero (no propagation) then CR0.eq is zero
+
+CR based version, TODO.