(no commit message)

[libreriscv.git] / openpower / sv / vector_swizzle.mdwn

diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn
index 4b6688a19128044333aaf1646073c80589e9c99d..34322e8a4677a4674e8f0cd7f61a182893beced0 100644 (file)
--- a/openpower/sv/vector_swizzle.mdwn
+++ b/openpower/sv/vector_swizzle.mdwn
@@ -1,6 +1,9 @@
+[[!tag standards]]
+
 # SV Vector Prefix Swizzle
 
-<https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://libre-soc.org/simple_v_extension/specification/mv.x/>
 
 3D GPU operations on batches of vec2, vec3 and vec4 often require re-ordering of the elements in an "out of lane" fashion with respect to standard high performance non-GPU-centric Vector Processors.  Examples include:
 
@@ -38,3 +41,9 @@ There is also benefit to encoding some useful immediates into src operands, on a
   - 0 (or 0.0)
   - 1 (or 1.0)
   - -1 (or -1.0) or some other option?
+
+# mv.swizzle
+
+is definitely needed.  TBD encoding.  requires 1 src, 1 dest, and 12 bits immediate minimum.
+
+[[sv/mv.swizzle]]