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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 223d3befb4815771f007810d32f678c4be0f85ff..0769fbe1e4ed18dc83f831e68e7b9f0b1d7e01d4 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -38,7 +38,7 @@ Fundamental design principles:
   (termed "preserving Program Order")
 * Specifically designed to be Precise-Interruptible at all times
   (many Vector ISAs have operations which, due to higher internal
-  accuracy or other complexity, must be effectively atomic for
+  accuracy or other complexity, must be effectively atomic only for
   the full Vector operation's duration, adversely affecting interrupt
   response latency, or be abandoned and started again)
 * Augments ("tags") existing instructions, providing Vectorisation
@@ -350,13 +350,16 @@ However when combined with the bitmanip scalar instructions
 requiring two Major opcodes this would come to a grand total of 3 precious
 Major opcodes. On balance, then, sacrificing 25% of EXT001 is the "least
 difficult" choice.
+Alternative locations for SVP64
+Prefixing include EXT006 and EXT017, with EXT006 being most favourable
+as there is room for future expansion.
 
 Note also that EXT022, the Official Architectural Sandbox area
 available for "Custom non-approved purposes" according to the Power
 ISA Spec,
 is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU.  Akthough the wording of the Power ISA
+a Hybrid 3D CPU-VPU-GPU.  Although the wording of the Power ISA
 Specification leaves open the *possibility* of not needing to
 propose ISA Extensions to the ISA WG, it is clear that EXT022
 is an inappropriate location for a large high-profile Extension