(termed "preserving Program Order")
* Specifically designed to be Precise-Interruptible at all times
(many Vector ISAs have operations which, due to higher internal
- accuracy or other complexity, must be effectively atomic for
+ accuracy or other complexity, must be effectively atomic only for
the full Vector operation's duration, adversely affecting interrupt
response latency, or be abandoned and started again)
* Augments ("tags") existing instructions, providing Vectorisation
different results on different hardware (present or future)
* Thirdly, that implementors are not permitted to either add
arbitrary features nor implement features in an incompatible
- way.
+ way. *(Performance may differ, but differing results are
+ not permitted)*.
* Fourthly, that any part of Simple-V not implemented by
a lower Compliancy Level is *required* to raise an illegal
- instruction trap.
+ instruction trap (allowing soft-emulation).
* Fifthly, that any `UNDEFINED` behaviour for practical implementation
reasons is clearly documented for both programmers and hardware
implementors.
requiring two Major opcodes this would come to a grand total of 3 precious
Major opcodes. On balance, then, sacrificing 25% of EXT001 is the "least
difficult" choice.
+Alternative locations for SVP64
+Prefixing include EXT006 and EXT017, with EXT006 being most favourable
+as there is room for future expansion.
Note also that EXT022, the Official Architectural Sandbox area
available for "Custom non-approved purposes" according to the Power
ISA Spec,
is under severe design pressure as it is insufficient to hold
the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU. Akthough the wording of the Power ISA
+a Hybrid 3D CPU-VPU-GPU. Although the wording of the Power ISA
Specification leaves open the *possibility* of not needing to
propose ISA Extensions to the ISA WG, it is clear that EXT022
is an inappropriate location for a large high-profile Extension