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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 0769fbe1e4ed18dc83f831e68e7b9f0b1d7e01d4..1db110afd3c9c4a04800fab73379982b48dffbdf 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -138,6 +138,7 @@ Pages being developed and examples
   or are not immediately apparent despite the RISC paradigm
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
 * [[sv/sprs]] SPRs
+* [[sv/rfc]] RFCs to the [OPF ISA WG](https://openpower.foundation/isarfc/)
 
 SVP64 "Modes":