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[libreriscv.git]
/
openpower
/
sv.mdwn
diff --git
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b/openpower/sv.mdwn
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openpower/sv.mdwn
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openpower/sv.mdwn
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Pages being developed and examples
or are not immediately apparent despite the RISC paradigm
* [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
* [[sv/sprs]] SPRs
+* [[sv/rfc]] RFCs to the [OPF ISA WG](https://openpower.foundation/isarfc/)
SVP64 "Modes":