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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bf3634b33424186b8dddf20c7ecd27a424e75256..1db110afd3c9c4a04800fab73379982b48dffbdf 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -38,7 +38,7 @@ Fundamental design principles:
   (termed "preserving Program Order")
 * Specifically designed to be Precise-Interruptible at all times
   (many Vector ISAs have operations which, due to higher internal
-  accuracy or other complexity, must be effectively atomic for
+  accuracy or other complexity, must be effectively atomic only for
   the full Vector operation's duration, adversely affecting interrupt
   response latency, or be abandoned and started again)
 * Augments ("tags") existing instructions, providing Vectorisation
@@ -138,6 +138,7 @@ Pages being developed and examples
   or are not immediately apparent despite the RISC paradigm
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
 * [[sv/sprs]] SPRs
+* [[sv/rfc]] RFCs to the [OPF ISA WG](https://openpower.foundation/isarfc/)
 
 SVP64 "Modes":
 
@@ -177,10 +178,11 @@ It requires certain guarantees to be provided.
   different results on different hardware (present or future)
 * Thirdly, that implementors are not permitted to either add
   arbitrary features nor implement features in an incompatible
-  way.
+  way. *(Performance may differ, but differing results are
+  not permitted)*.
 * Fourthly, that any part of Simple-V not implemented by
   a lower Compliancy Level is *required* to raise an illegal
-  instruction trap.
+  instruction trap (allowing soft-emulation).
 * Fifthly, that any `UNDEFINED` behaviour for practical implementation
   reasons is clearly documented for both programmers and hardware
   implementors.
@@ -349,13 +351,16 @@ However when combined with the bitmanip scalar instructions
 requiring two Major opcodes this would come to a grand total of 3 precious
 Major opcodes. On balance, then, sacrificing 25% of EXT001 is the "least
 difficult" choice.
+Alternative locations for SVP64
+Prefixing include EXT006 and EXT017, with EXT006 being most favourable
+as there is room for future expansion.
 
 Note also that EXT022, the Official Architectural Sandbox area
 available for "Custom non-approved purposes" according to the Power
 ISA Spec,
 is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU.  Akthough the wording of the Power ISA
+a Hybrid 3D CPU-VPU-GPU.  Although the wording of the Power ISA
 Specification leaves open the *possibility* of not needing to
 propose ISA Extensions to the ISA WG, it is clear that EXT022
 is an inappropriate location for a large high-profile Extension