+[[!tag standards]]
+
# Simple-V Vectorisation for the OpenPOWER ISA
+**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
+
<https://bugs.libre-soc.org/show_bug.cgi?id=213>
Fundamental design principles:
Pages being developed and examples
* [[sv/overview]] explaining the basics.
-* [[sv/predication]]
+* [[sv/predication]] discussion on predication concepts
* [[sv/masked_vector_chaining]]
* [[sv/discussion]]
* [[sv/example_dep_matrices]]
* [[sv/cr_int_predication]]
* [[sv/setvl]]
* [[sv/svp64]]
-* [[sv/ldst]]
-* [[sv/sprs]]
+* [[sv/ldst]] Load and Store
+* [[sv/sprs]] SPRs
* [[sv/bitmanip]]
-* [[sv/propagation]]
+* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
+* [[sv/propagation]] Context propagation including svp64, swizzle and remap
* [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
* [[sv/av_opcodes]] scalar opcodes for Audio/Video
* [[sv/byteswap]]
+* TODO: OpenPOWER [[openpower/transcendentals]]
Additional links: