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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index f6707727621a4f8f56895e728a6ce555d2bb3772..45dc32ad38163b3bba96c0d97fa257a87e271069 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -1,5 +1,9 @@
+[[!tag standards]]
+
 # Simple-V Vectorisation for the OpenPOWER ISA
 
+**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
+
 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 
 Fundamental design principles:
@@ -17,12 +21,14 @@ Advantages of these design principles:
 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
 * Completely wipes not just SIMD opcode proliferation off the
-  map but off of Vectorisation ISAs as well.  No more separate Vector
+  map (SIMD is O(N^6) opcode proliferation)
+  but off of Vectorisation ISAs as well.  No more separate Vector
   instructions.
 
 Pages being developed and examples
 
-* [[sv/predication]]
+* [[sv/overview]] explaining the basics.
+* [[sv/predication]] discussion on predication concepts
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]
 * [[sv/example_dep_matrices]]
@@ -32,12 +38,24 @@ Pages being developed and examples
 * [[sv/vector_swizzle]]
 * [[sv/mv.swizzle]]
 * [[sv/mv.x]]
+* [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
 * [[sv/mv.vec]] move to and from vec2/3/4
 * [[sv/16_bit_compressed]]
 * [[sv/toc_data_pointer]]
 * [[sv/cr_int_predication]]
 * [[sv/setvl]]
-* [[sv/svp_rewrite]]
-* [[sv/ldst]]
-* [[sv/sprs]] 
+* [[sv/svp64]]
+* [[sv/ldst]] Load and Store
+* [[sv/sprs]] SPRs
+* [[sv/bitmanip]]
+* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
+* [[sv/propagation]] Context propagation including svp64, swizzle and remap
+* [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
+* [[sv/byteswap]]
+* TODO: OpenPOWER [[openpower/transcendentals]]
+
+Additional links:
+
+* <https://www.sigarch.org/simd-instructions-considered-harmful/>
+* [[simple_v_extension]] old (deprecated) version