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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 807e6a4cd643daad746ca723a7b4a3101dca186d..5c1eab37951c1eca4898e8f0cc5f27cfac881a70 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -1,5 +1,9 @@
+[[!tag standards]]
+
 # Simple-V Vectorisation for the OpenPOWER ISA
 
+**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
+
 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 
 Fundamental design principles:
@@ -9,7 +13,9 @@ Fundamental design principles:
 * Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions
   (termed "preserving Program Order")
 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
-* Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
+* Does not modify or deviate from the underlying scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
+* Designed for Supercomputing: avoids creating significant sequential
+dependency hazards, allowing high performance superscalar microarchitectures to be deployed.
 
 Advantages of these design principles:
 
@@ -23,27 +29,48 @@ Advantages of these design principles:
 
 Pages being developed and examples
 
-* [[sv/predication]]
+* [[sv/overview]] explaining the basics.
+* [[sv/implementation]] implementation planning and coordination
+* [[sv/svp64]] contains the packet-format *only*
+* [[sv/setvl]] the Cray-style "Vector Length" instruction
+* [[sv/predication]] discussion on predication concepts
+* [[sv/cr_int_predication]] instructions needed for effective predication
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]
 * [[sv/example_dep_matrices]]
-* [[sv/prefix]]
 * [[sv/major_opcode_allocation]]
 * [[opcode_regs_deduped]]
 * [[sv/vector_swizzle]]
+* [[sv/register_type_tags]]
 * [[sv/mv.swizzle]]
 * [[sv/mv.x]]
+* [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs
+* [[sv/cr_ops]] - SVP64 Condition Register ops: Guidelines
+ on Vectorisation of any v3.0B base operations which return
+ or modify a Condition Register bit or field.
+* [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
+* [[sv/fclass]] detect class of FP numbers
+* [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
 * [[sv/mv.vec]] move to and from vec2/3/4
-* [[sv/16_bit_compressed]]
-* [[sv/toc_data_pointer]]
-* [[sv/cr_int_predication]]
-* [[sv/setvl]]
-* [[sv/svp_rewrite]]
-* [[sv/ldst]]
-* [[sv/sprs]] 
+* [[sv/16_bit_compressed]] experimental
+* [[sv/toc_data_pointer]] experimental
+* [[sv/ldst]] Load and Store
+* [[sv/sprs]] SPRs
+* [[sv/bitmanip]]
+* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
+* [[sv/propagation]] Context propagation including svp64, swizzle and remap
+* [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
+* [[sv/byteswap]]
+* TODO: OpenPOWER [[openpower/transcendentals]]
 
 Additional links:
 
 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
 * [[simple_v_extension]] old (deprecated) version
+* [[openpower/sv/llvm]]
+
+Obligatory Dilbert:
+
+<img src="https://assets.amuniversal.com/7fada35026ca01393d3d005056a9545d" width="600" />
+