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[libreriscv.git] / openpower / sv.mdwn

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 4e68995af8a8582ca33de99aff63dcc6e92ab12d..fe33fc2066b578e41628723489550a86fbfa6578 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -1,5 +1,9 @@
+[[!tag standards]]
+
 # Simple-V Vectorisation for the OpenPOWER ISA
 
+**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
+
 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 
 Fundamental design principles:
@@ -24,30 +28,33 @@ Advantages of these design principles:
 Pages being developed and examples
 
 * [[sv/overview]] explaining the basics.
-* [[sv/predication]]
+* [[sv/implementation]] implementation planning and coordination
+* [[sv/svp64]] contains the packet-format *only*
+* [[sv/setvl]] the Cray-style "Vector Length" instruction
+* [[sv/predication]] discussion on predication concepts
+* [[sv/cr_int_predication]] instructions needed for effective predication
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]
 * [[sv/example_dep_matrices]]
-* [[sv/prefix]]
 * [[sv/major_opcode_allocation]]
 * [[opcode_regs_deduped]]
 * [[sv/vector_swizzle]]
 * [[sv/mv.swizzle]]
 * [[sv/mv.x]]
 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
+* [[sv/fclass]] detect class of FP numbers
 * [[sv/mv.vec]] move to and from vec2/3/4
-* [[sv/16_bit_compressed]]
-* [[sv/toc_data_pointer]]
-* [[sv/cr_int_predication]]
-* [[sv/setvl]]
-* [[sv/svp64]]
-* [[sv/ldst]]
-* [[sv/sprs]]
+* [[sv/16_bit_compressed]] experimental
+* [[sv/toc_data_pointer]] experimental
+* [[sv/ldst]] Load and Store
+* [[sv/sprs]] SPRs
 * [[sv/bitmanip]]
+* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * [[sv/byteswap]]
+* TODO: OpenPOWER [[openpower/transcendentals]]
 
 Additional links: