reorganise docs (shorten URL)

[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 0287811158cd5ecfdd7c5518d27ad5ab0b5dd327..0832f97fd2509c80d4b2d9d55c05fdaa915ae079 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -1,8 +1,9 @@
 # OpenPOWER
+
 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
 This evolved to a specification known as the Power ISA. In 2019 IBM made the Power ISA [[!wikipedia Open_source]] to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]].
 
-Libre-soc is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted.
+Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER is designed for high performance.
 
 # Evaluation
 
@@ -172,12 +173,3 @@ Store activation length in a CSR.
 
 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 
-# RISCV userspace
-
-Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
-
-the exception entry point:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
-
-the rest of the context switch code is in a different file:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>