stw/std/std/stb must be SRC-RA and SRC-RS

[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 96526baf24664e88d17cefc4ec61b59a0070013a..0832f97fd2509c80d4b2d9d55c05fdaa915ae079 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -1,3 +1,10 @@
+# OpenPOWER
+
+In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
+This evolved to a specification known as the Power ISA. In 2019 IBM made the Power ISA [[!wikipedia Open_source]] to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]].
+
+Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER is designed for high performance.
+
 # Evaluation
 
 EULA released! looks good.
@@ -11,6 +18,7 @@ Links
 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
 * [[openpower/gem5]]
 * [[openpower/sv]]
+* [[openpower/simd_vsx]]
 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
 * [[openpower/pearpc]]
 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
@@ -47,7 +55,7 @@ Summary
 
 # SimpleV
 
-see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
+see [[openpower/sv]].
 SimpleV: a "hardware for-loop" which involves type-casting (both) the
 register files to "a sequence of elements".  The **one** instruction
 (an unmodified **scalar** instruction) is interpreted as a *hardware
@@ -64,7 +72,7 @@ Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR
 
 ## Carry
 
-SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
 
 # Integer Overflow / Saturate
 
@@ -165,12 +173,3 @@ Store activation length in a CSR.
 
 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 
-# RISCV userspace
-
-Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
-
-the exception entry point:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
-
-the rest of the context switch code is in a different file:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>