Links
+* OpenPOWER Membership
+ <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
+* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
* [[openpower/isatables]]
-* https://forums.raptorcs.com/
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
-* http://bugs.libre-riscv.org/show_bug.cgi?id=179
-* https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
-* https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
+* [[3d_gpu/architecture/decoder]]
+* <https://forums.raptorcs.com/>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
+* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
+* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+
+PowerPC Unit Tests
+
+* <https://github.com/lioncash/DolphinPPCTests>
+* <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
Summary
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
* Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors or Opcode 60 VSX
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
* Avoidable legacy opcodes
# SimpleV
saving hugely on both hardware and compiler development time when
the concept is dropped on top of a pre-existing ISA.
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
# Integer Overflow / Saturate
Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
* OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
* OP 000-110 and 000-111 for VBLOCK. 11 bits available.
+Note that this requires BE instruction encoding (separate from
+data BE/LE encoding). BE encoding always places the major opcode in
+the first 2 bytes of the raw (uninterpreted) sequential instruction
+byte stream.
+
+Thus in BE-instruction-mode, the first 2 bytes may be analysed to
+detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
+64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
+
+It is not possible to distinguish LE-encoded 32-bit instructions
+from LE-encoded 16-bit instructions because in LE-encoded 32-bit
+instructions, the opcode falls into:
+
+* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
+ byte stream for a 32-bit instruction
+* bytes 0 and 1 for a 16-bit Compressed instruction
+* bytes 4 and 5 for a 48-bit SVP P48
+* bytes 6 and 7 for a 64-bit SVP P64
+
+Clearly this is an impossible situation, therefore BE is the only
+option. Note: *this is completely separate from BE/LE for data*
+
# Compressed 16
Further "escape-sequencing".
Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>
projects / libreriscv.git / blobdiff