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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 962aa81f0e9299c47138e148e65e2d4d0f7f1fbd..4506c9653e12c9b4bbead3681161f9cc7172425d 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -9,11 +9,18 @@ i5, i7, i9 etc. and are frequently conflated with versions of the OpenPOWER ISA
 Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER, thanks to IBM's involvement,
 is designed for high performance.
 
+See wikipedia page 
+<https://en.m.wikipedia.org/wiki/Power_ISA>
+
+very useful resource describing all assembly instructions
+<https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
+
 # Evaluation
 
 EULA released! looks good.
+<https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/>
 
-Links
+# Links
 
 * OpenPOWER Membership
   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
@@ -56,6 +63,7 @@ Summary
 * Opcode 4 Signal Processing (SPE)
 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
 * Avoidable legacy opcodes
+* SIMD. it's awful.
 
 # SimpleV