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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 0287811158cd5ecfdd7c5518d27ad5ab0b5dd327..4506c9653e12c9b4bbead3681161f9cc7172425d 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -1,14 +1,26 @@
 # OpenPOWER
+
 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
-This evolved to a specification known as the Power ISA. In 2019 IBM made the Power ISA [[!wikipedia Open_source]] to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]].
+This evolved to a specification known as the OpenPOWER ISA. In 2019 IBM made the OpenPOWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors 
+happen to implement what is now known as the OpenPOWER ISA. The names
+POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel
+i5, i7, i9 etc. and are frequently conflated with versions of the OpenPOWER ISA (v2.08, v3.0, v3.1).
+
+Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER, thanks to IBM's involvement,
+is designed for high performance.
+
+See wikipedia page 
+<https://en.m.wikipedia.org/wiki/Power_ISA>
 
-Libre-soc is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted.
+very useful resource describing all assembly instructions
+<https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
 
 # Evaluation
 
 EULA released! looks good.
+<https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/>
 
-Links
+# Links
 
 * OpenPOWER Membership
   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
@@ -51,6 +63,7 @@ Summary
 * Opcode 4 Signal Processing (SPE)
 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
 * Avoidable legacy opcodes
+* SIMD. it's awful.
 
 # SimpleV
 
@@ -172,12 +185,3 @@ Store activation length in a CSR.
 
 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 
-# RISCV userspace
-
-Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
-
-the exception entry point:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
-
-the rest of the context switch code is in a different file:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>