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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index e1f717826c39c3b2b1092dd2e765c084ec528bab..4b0a9535aadea527e1641c8d00cf0cebab11ddd3 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -1,5 +1,11 @@
 # Evaluation
 
+EULA released! looks good.
+
+* https://forums.raptorcs.com/
+* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
+* http://bugs.libre-riscv.org/show_bug.cgi?id=179
+
 * FP32 is converted to FP64. Requires SV to be active.
 * FP16 needed
 * FCVT between 16/32/64 needed
@@ -21,6 +27,8 @@ Doesn't exist in Power, need to work out suitable opcodes, basically means dupli
 
 Usually done with a fmt field, 2 bit, last one is FP128
 
+idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
+
 # Escape Sequencing
 
 Absolutely critical, also to have official endorsement from OpenPower Foundation.