* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
* [[openpower/gem5]]
* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
* [[3d_gpu/architecture/decoder]]
* <https://forums.raptorcs.com/>
* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
* A processor that is fundamentally incompatible (noncompliant) with Power.
(**escape-sequencing requires and guarantees compatibility**).
* Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors or Opcode 60 VSX
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
* Avoidable legacy opcodes
# SimpleV