# Evaluation
-* FP32 is converted to FP64. Requires SV to be active.
+EULA released! looks good.
+
+Links
+
+* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
+* [[openpower/isatables]]
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/pearpc]]
+* [[3d_gpu/architecture/decoder]]
+* <https://forums.raptorcs.com/>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
+* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
+* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+
+PowerPC Unit Tests
+
+* <https://github.com/lioncash/DolphinPPCTests>
+* <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
+
+Summary
+
+* FP32 is converted to FP64. Requires SimpleV to be active.
* FP16 needed
+* transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
* needs escape sequencing (ISAMUX/NS)
+# What we are *NOT* doing:
+
+* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
+* Opcode 4 Signal Processing (SPE)
+* Opcode 4 Vectors or Opcode 60 VSX
+* Avoidable legacy opcodes
+
+# SimpleV
+
+see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
+SimpleV: a "hardware for-loop" which involves type-casting (both) the
+register files to "a sequence of elements". The **one** instruction
+(an unmodified **scalar** instruction) is interpreted as a *hardware
+for-loop* that issues **multiple** internal instructions with
+sequentially-incrementing register numbers.
+
+Thus it is completely unnecessary to add any vector opcodes - at all -
+saving hugely on both hardware and compiler development time when
+the concept is dropped on top of a pre-existing ISA.
+
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
+# Integer Overflow / Saturate
+
+Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
+
# atomics
Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
# FP16
-Doesn't exist in Power (does - as VLE?), need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
+Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
Usually done with a fmt field, 2 bit, last one is FP128
+idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise. can also be done as C instruction, only needs 4 bits to specify.
+
# Escape Sequencing
-Absolutely critical, also to have official endorsement from OpenPower Foundation.
+aka "ISAMUX/NS". Absolutely critical, also to have official endorsement
+from OpenPower Foundation.
This will allow extending ISA (see ISAMUX/NS) in a clean fashion
+(including for and by OpenPower Foundation)
+
+## Branches in namespaces
+
+Branches are fine as it is up to the compiler to decide whether to let the
+ISAMUX/NS/escape-sequence countdown run out.
+
+This is all a software / compiler / ABI issue.
+
+## Function calls in namespaces
+
+Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
+
+If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
+
+All of this is a software issue (compiler / ABI).
# Compressed, 48, 64, VBLOCK
-TODO investigate Power VLE
+TODO investigate Power VLE (Freescale doc Ref 314-68105)
-Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the entire row, 2 bits instead of 3.
+Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
+entire row, 2 bits instead of 3. greatly simplifies decoder.
* OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
* OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
# Compressed 16
-Only 11 bits. Idea: have "pages" where one instruction selects the page number. It also specifies for how long that page is activated (terminated on a branch)
+Further "escape-sequencing".
+
+Only 11 bits available. Idea: have "pages" where one instruction selects
+the page number. It also specifies for how long that page is activated
+(terminated on a branch)
The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
-## Branches
-
-Branches are fine as it is up to the compiler to decide whether to let the countdown run out.
+# RISCV userspace
-This is all a software / compiler / ABI issue.
+Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
-## Function calls.
-
-Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
-
-If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
-
-All of this is a software issue (compiler / ABI).
+the exception entry point:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+the rest of the context switch code is in a different file:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
projects / libreriscv.git / blobdiff