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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 28fe6291534bd60b5c1e21d5afcba985e7d81110..930ccda457f81b05f7bfbbbaea138acd7d02fedd 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,7 +4,12 @@ EULA released! looks good.
 
 Links
 
+* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
 * [[openpower/isatables]]
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/pearpc]]
+* [[3d_gpu/architecture/decoder]]
 * <https://forums.raptorcs.com/>
 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
@@ -12,6 +17,11 @@ Links
 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
 
+PowerPC Unit Tests
+
+* <https://github.com/lioncash/DolphinPPCTests>
+* <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
+
 Summary
 
 * FP32 is converted to FP64. Requires SimpleV to be active.
@@ -43,6 +53,14 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
 saving hugely on both hardware and compiler development time when
 the concept is dropped on top of a pre-existing ISA.
 
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
 # Integer Overflow / Saturate
 
 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.