Fix size of picture

[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 6c44e4142115c8411cf6ae65b7a847af78177dc2..930ccda457f81b05f7bfbbbaea138acd7d02fedd 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,12 +4,23 @@ EULA released! looks good.
 
 Links
 
-* https://forums.raptorcs.com/
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
-* http://bugs.libre-riscv.org/show_bug.cgi?id=179
-* https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
-* https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
+* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
+* [[openpower/isatables]]
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/pearpc]]
+* [[3d_gpu/architecture/decoder]]
+* <https://forums.raptorcs.com/>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
+* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
+* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
+* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+
+PowerPC Unit Tests
+
+* <https://github.com/lioncash/DolphinPPCTests>
+* <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
 
 Summary
 
@@ -21,6 +32,14 @@ Summary
 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
 * needs escape sequencing (ISAMUX/NS)
 
+# What we are *NOT* doing:
+
+* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
+* Opcode 4 Signal Processing (SPE)
+* Opcode 4 Vectors or Opcode 60 VSX
+* Avoidable legacy opcodes
+
 # SimpleV
 
 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
@@ -34,6 +53,18 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
 saving hugely on both hardware and compiler development time when
 the concept is dropped on top of a pre-existing ISA.
 
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
+# Integer Overflow / Saturate
+
+Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
+
 # atomics
 
 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.