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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 930ccda457f81b05f7bfbbbaea138acd7d02fedd..96526baf24664e88d17cefc4ec61b59a0070013a 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,11 +4,16 @@ EULA released! looks good.
 
 Links
 
+* OpenPOWER Membership
+  <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
 * [[openpower/isatables]]
 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
 * [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
 * [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
 * [[3d_gpu/architecture/decoder]]
 * <https://forums.raptorcs.com/>
 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
@@ -30,14 +35,14 @@ Summary
 * FCVT between 16/32/64 needed
 * c++11 atomics not very efficient
 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
 
 # What we are *NOT* doing:
 
 * A processor that is fundamentally incompatible (noncompliant) with Power.
  (**escape-sequencing requires and guarantees compatibility**).
 * Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors or Opcode 60 VSX
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
 * Avoidable legacy opcodes
 
 # SimpleV
@@ -116,6 +121,28 @@ entire row, 2 bits instead of 3.  greatly simplifies decoder.
 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 
+Note that this requires BE instruction encoding (separate from
+data BE/LE encoding).  BE encoding always places the major opcode in
+the first 2 bytes of the raw (uninterpreted) sequential instruction
+byte stream.
+
+Thus in BE-instruction-mode, the first 2 bytes may be analysed to
+detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
+64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
+
+It is not possible to distinguish LE-encoded 32-bit instructions
+from LE-encoded 16-bit instructions because in LE-encoded 32-bit
+instructions, the opcode falls into:
+
+* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
+  byte stream for a 32-bit instruction
+* bytes 0 and 1 for a 16-bit Compressed instruction
+* bytes 4 and 5 for a 48-bit SVP P48
+* bytes 6 and 7 for a 64-bit SVP P64
+
+Clearly this is an impossible situation, therefore BE is the only
+option.  Note: *this is completely separate from BE/LE for data*
+
 # Compressed 16
 
 Further "escape-sequencing".
@@ -143,7 +170,7 @@ Requirements are to have one instruction in each subpage which resets all the wa
 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 
 the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 
 the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>