Links
+* OpenPOWER Membership
+ <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
* [[openpower/isatables]]
* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
* [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
* [[3d_gpu/architecture/decoder]]
* <https://forums.raptorcs.com/>
* <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>