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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 5e534f619e4b55f7659b12415aa080d6479dc827..96526baf24664e88d17cefc4ec61b59a0070013a 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,10 +4,14 @@ EULA released! looks good.
 
 Links
 
+* OpenPOWER Membership
+  <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
 * [[openpower/isatables]]
 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
 * [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
 * [[openpower/pearpc]]
 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
 * [[3d_gpu/architecture/decoder]]
@@ -166,7 +170,7 @@ Requirements are to have one instruction in each subpage which resets all the wa
 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 
 the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 
 the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>