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[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index 200d924c344f9122f70e4d593f96bc0bc16107df..a197996109aca7f1b7c9792a99ced029dbd37852 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -21,6 +21,8 @@ Doesn't exist in Power, need to work out suitable opcodes, basically means dupli
 
 Usually done with a fmt field, 2 bit, last one is FP128
 
+idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
+
 # Escape Sequencing
 
 Absolutely critical, also to have official endorsement from OpenPower Foundation.
@@ -70,3 +72,12 @@ If certain alternative configs are expected, they are part of the function ABI w
 
 All of this is a software issue (compiler / ABI).
 
+# RISCV userspace
+
+Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
+
+the exception entry point:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+
+the rest of the context switch code is in a different file:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589