* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
* [[openpower/gem5]]
* [[openpower/sv]]
+* [[openpower/prefix_codes]] Decode/encode prefix-codes, used by JPEG, DEFLATE, etc.
* [[openpower/opcode_regs_deduped]]
* [[openpower/simd_vsx]]
* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
saving hugely on both hardware and compiler development time when
the concept is dropped on top of a pre-existing ISA.
-## Condition Registers
-
-Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
-
-## Carry
-
-SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
-
# Integer Overflow / Saturate
Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.