add architecture comparison table

[libreriscv.git] / openpower.mdwn

diff --git a/openpower.mdwn b/openpower.mdwn
index ccf8b1d28e0bdadc5aaced28acc1e46867a4b0c1..e1f717826c39c3b2b1092dd2e765c084ec528bab 100644 (file)
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -17,7 +17,7 @@ Hot loops contain significant instruction count, really need new c++11 atomics.
 
 # FP16
 
-Doesn't exist in Power (does - as VLE?), need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
+Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
 
 Usually done with a fmt field, 2 bit, last one is FP128
 
@@ -29,7 +29,7 @@ This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 
 # Compressed, 48, 64, VBLOCK
 
-TODO investigate Power VLE
+TODO investigate Power VLE (Freescale doc Ref 314-68105)
 
 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the entire row, 2 bits instead of 3.
 
@@ -70,3 +70,12 @@ If certain alternative configs are expected, they are part of the function ABI w
 
 All of this is a software issue (compiler / ABI).
 
+# RISCV userspace
+
+Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
+
+the exception entry point:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+
+the rest of the context switch code is in a different file:
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589