}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
- formal_cell->setPort(ID(A), wire);
+ formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
- formal_cell->setPort(ID(EN), State::S1);
+ formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
}
else {
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
- formal_cell->setPort(ID(EN), enable_wire);
+ formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
}
}
struct AddPass : public Pass {
AddPass() : Pass("add", "add objects to the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("Add module[s] with the specified name[s].\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string command;
std::string arg_name;
log_assert(module != nullptr);
if (!design->selected_whole_module(module->name))
continue;
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_bool_attribute(ID::blackbox))
continue;
selected_anything = true;