Merge pull request #2168 from whitequark/assert-unused-exprs

[yosys.git] / passes / cmds / add.cc

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index c49b8bf5d5e770f98db0a97049dbb7dc1334b1e3..a2f4a91000f8e6565c4bcf7b75a6e800a190dfff 100644 (file)
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -42,9 +42,9 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
        }
        else {
                RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
-               formal_cell->setPort(ID(A), wire);
+               formal_cell->setPort(ID::A, wire);
                if(enable_name == "") {
-                       formal_cell->setPort(ID(EN), State::S1);
+                       formal_cell->setPort(ID::EN, State::S1);
                        log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
                }
                else {
@@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
                        if(enable_wire == nullptr)
                                log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
 
-                       formal_cell->setPort(ID(EN), enable_wire);
+                       formal_cell->setPort(ID::EN, enable_wire);
                        log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
                }
        }
@@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 
 struct AddPass : public Pass {
        AddPass() : Pass("add", "add objects to the design") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -150,7 +150,7 @@ struct AddPass : public Pass {
                log("Add module[s] with the specified name[s].\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                std::string command;
                std::string arg_name;
@@ -212,7 +212,7 @@ struct AddPass : public Pass {
                        log_assert(module != nullptr);
                        if (!design->selected_whole_module(module->name))
                                continue;
-                       if (module->get_bool_attribute("\\blackbox"))
+                       if (module->get_bool_attribute(ID::blackbox))
                                continue;
 
                        selected_anything = true;