Merge pull request #2168 from whitequark/assert-unused-exprs

[yosys.git] / passes / cmds / delete.cc

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 5822c09f8888c5b7b6c0566ed68b3dc4f40191ee..684fa37b047a6938bfb410faab48aaef66e909e1 100644 (file)
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct DeletePass : public Pass {
        DeletePass() : Pass("delete", "delete objects in the design") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -40,7 +40,7 @@ struct DeletePass : public Pass {
                log("selected wires, thus 'deleting' module ports.\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                bool flag_input = false;
                bool flag_output = false;
@@ -65,27 +65,24 @@ struct DeletePass : public Pass {
                }
                extra_args(args, argidx, design);
 
-               std::vector<RTLIL::IdString> delete_mods;
-
-               for (auto &mod_it : design->modules_)
+               std::vector<RTLIL::Module *> delete_mods;
+               for (auto module : design->modules())
                {
-                       if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
-                               delete_mods.push_back(mod_it.first);
+                       if (design->selected_whole_module(module->name) && !flag_input && !flag_output) {
+                               delete_mods.push_back(module);
                                continue;
                        }
 
-                       if (!design->selected_module(mod_it.first))
+                       if (!design->selected_module(module->name))
                                continue;
 
-                       RTLIL::Module *module = mod_it.second;
-
                        if (flag_input || flag_output) {
-                               for (auto &it : module->wires_)
-                                       if (design->selected(module, it.second)) {
+                               for (auto wire : module->wires())
+                                       if (design->selected(module, wire)) {
                                                if (flag_input)
-                                                       it.second->port_input = false;
+                                                       wire->port_input = false;
                                                if (flag_output)
-                                                       it.second->port_output = false;
+                                                       wire->port_output = false;
                                        }
                                module->fixup_ports();
                                continue;
@@ -96,20 +93,19 @@ struct DeletePass : public Pass {
                        pool<RTLIL::IdString> delete_procs;
                        pool<RTLIL::IdString> delete_mems;
 
-                       for (auto &it : module->wires_)
-                               if (design->selected(module, it.second))
-                                       delete_wires.insert(it.second);
+                       for (auto wire : module->selected_wires())
+                               delete_wires.insert(wire);
 
                        for (auto &it : module->memories)
                                if (design->selected(module, it.second))
                                        delete_mems.insert(it.first);
 
-                       for (auto &it : module->cells_) {
-                               if (design->selected(module, it.second))
-                                       delete_cells.insert(it.second);
-                               if (it.second->type.in("$memrd", "$memwr") &&
-                                               delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
-                                       delete_cells.insert(it.second);
+                       for (auto cell : module->cells()) {
+                               if (design->selected(module, cell))
+                                       delete_cells.insert(cell);
+                               if (cell->type.in(ID($memrd), ID($memwr)) &&
+                                               delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0)
+                                       delete_cells.insert(cell);
                        }
 
                        for (auto &it : module->processes)
@@ -134,9 +130,8 @@ struct DeletePass : public Pass {
                        module->fixup_ports();
                }
 
-               for (auto &it : delete_mods) {
-                       delete design->modules_.at(it);
-                       design->modules_.erase(it);
+               for (auto mod : delete_mods) {
+                       design->remove(mod);
                }
        }
 } DeletePass;