* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
*
*/
-#include "kernel/register.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
-
-struct DeleteWireWorker
-{
- RTLIL::Module *module;
- std::set<std::string> *delete_wires_p;
-
- void operator()(RTLIL::SigSpec &sig) {
- sig.optimize();
- for (auto &c : sig.chunks_rw())
- if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
- c.wire = module->addWire(NEW_ID, c.width);
- c.offset = 0;
- }
- }
-};
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
- virtual void help()
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("selected wires, thus 'deleting' module ports.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_input = false;
bool flag_output = false;
}
extra_args(args, argidx, design);
- std::vector<std::string> delete_mods;
-
- for (auto &mod_it : design->modules)
+ std::vector<RTLIL::Module *> delete_mods;
+ for (auto module : design->modules())
{
- if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
- delete_mods.push_back(mod_it.first);
+ if (design->selected_whole_module(module->name) && !flag_input && !flag_output) {
+ delete_mods.push_back(module);
continue;
}
- if (!design->selected_module(mod_it.first))
+ if (!design->selected_module(module->name))
continue;
- RTLIL::Module *module = mod_it.second;
-
if (flag_input || flag_output) {
- for (auto &it : module->wires)
- if (design->selected(module, it.second)) {
+ for (auto wire : module->wires())
+ if (design->selected(module, wire)) {
if (flag_input)
- it.second->port_input = false;
+ wire->port_input = false;
if (flag_output)
- it.second->port_output = false;
+ wire->port_output = false;
}
module->fixup_ports();
continue;
}
- std::set<std::string> delete_wires;
- std::set<std::string> delete_cells;
- std::set<std::string> delete_procs;
- std::set<std::string> delete_mems;
+ pool<RTLIL::Wire*> delete_wires;
+ pool<RTLIL::Cell*> delete_cells;
+ pool<RTLIL::IdString> delete_procs;
+ pool<RTLIL::IdString> delete_mems;
- for (auto &it : module->wires)
- if (design->selected(module, it.second))
- delete_wires.insert(it.first);
+ for (auto wire : module->selected_wires())
+ delete_wires.insert(wire);
for (auto &it : module->memories)
if (design->selected(module, it.second))
delete_mems.insert(it.first);
- for (auto &it : module->cells) {
- if (design->selected(module, it.second))
- delete_cells.insert(it.first);
- if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
- delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
- delete_cells.insert(it.first);
+ for (auto cell : module->cells()) {
+ if (design->selected(module, cell))
+ delete_cells.insert(cell);
+ if (cell->type.in(ID($memrd), ID($memwr)) &&
+ delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0)
+ delete_cells.insert(cell);
}
for (auto &it : module->processes)
if (design->selected(module, it.second))
delete_procs.insert(it.first);
- DeleteWireWorker delete_wire_worker;
- delete_wire_worker.module = module;
- delete_wire_worker.delete_wires_p = &delete_wires;
- module->rewrite_sigspecs(delete_wire_worker);
-
- for (auto &it : delete_wires) {
- delete module->wires.at(it);
- module->wires.erase(it);
- }
-
for (auto &it : delete_mems) {
delete module->memories.at(it);
module->memories.erase(it);
}
- for (auto &it : delete_cells) {
- delete module->cells.at(it);
- module->cells.erase(it);
- }
+ for (auto &it : delete_cells)
+ module->remove(it);
for (auto &it : delete_procs) {
delete module->processes.at(it);
module->processes.erase(it);
}
+ module->remove(delete_wires);
+
module->fixup_ports();
}
- for (auto &it : delete_mods) {
- delete design->modules.at(it);
- design->modules.erase(it);
+ for (auto mod : delete_mods) {
+ design->remove(mod);
}
}
} DeletePass;
-
+
+PRIVATE_NAMESPACE_END
projects / yosys.git / blobdiff