SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

[yosys.git] / passes / cmds / delete.cc

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index c5aa196c6fb6afcc411e13d4c490a76c624b99e2..f433c4b4adc520dd5e11932746beec925b15c6ae 100644 (file)
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -28,7 +28,7 @@ struct DeleteWireWorker
 
        void operator()(RTLIL::SigSpec &sig) {
                sig.optimize();
-               for (auto &c : sig.chunks())
+               for (auto &c : sig.chunks_rw())
                        if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
                                c.wire = module->addWire(NEW_ID, c.width);
                                c.offset = 0;