Add new builtin FF types

[yosys.git] / passes / cmds / scatter.cc

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 7123ba9fb68ff6ddfb735effde6b2c5aafbf5176..a70dd308602877a4dc40e1ddacc35b69724c9b71 100644 (file)
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ScatterPass : public Pass {
        ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -41,30 +41,24 @@ struct ScatterPass : public Pass {
                log("Use the opt_clean command to get rid of the additional nets.\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                CellTypes ct(design);
                extra_args(args, 1, design);
 
-               for (auto &mod_it : design->modules_)
+               for (auto module : design->selected_modules())
                {
-                       if (!design->selected(mod_it.second))
-                               continue;
-
-                       for (auto &c : mod_it.second->cells_)
-                       for (auto &p : c.second->connections_)
-                       {
-                               RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
-
-                               if (ct.cell_output(c.second->type, p.first)) {
-                                       RTLIL::SigSig sigsig(p.second, wire);
-                                       mod_it.second->connect(sigsig);
-                               } else {
-                                       RTLIL::SigSig sigsig(wire, p.second);
-                                       mod_it.second->connect(sigsig);
+                       for (auto cell : module->cells()) {
+                               dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
+                               for (auto conn : cell->connections())
+                                       new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
+                               for (auto &it : new_connections) {
+                                       if (ct.cell_output(cell->type, it.first))
+                                               module->connect(RTLIL::SigSig(it.second.first, it.second.second));
+                                       else
+                                               module->connect(RTLIL::SigSig(it.second.second, it.second.first));
+                                       cell->setPort(it.first, it.second.second);
                                }
-
-                               p.second = wire;
                        }
                }
        }